| JULY 14-16, 2014

OIF launches new interconnect, 100G projects

Members of The Optical Internetworking Forum (OIF) agreed to launch three new projects at their most recent meeting in July. The projects include a Next Generation Interconnect Framework, an update of the OIF’s initial 100-Gbps integrated coherent receiver, and a multi-link gearbox (MLG) for 10 streams of data to travel through a 4 x 25-Gbps link and be recovered in their original form on the receive end.

OIF board member Jeff Hutchins told Lightwave that the Next Generation Interconnect Framework is an exploratory project to determine what will come after the OIF wraps up the CEI-28 interface. The project will consider interconnects within a blade, backplanes, and chassis to chassis. The project members will consider both electrical and optical technologies, Hutchins said, as the aim for a new set of implementation agreements (IAs).

The Generation 2.0 Intradyne Coherence Receiver (Gen-2 ICR) project has a much narrower focus – an IA that will drive cost and power reduction from the Gen-1 ICR IA (OIF-DPC-RX-01.0 IA) specifications. These first-generation devices are just now being implemented, and Hutchins says that project members have no shortage of ideas in terms of how to proceed with the second generation. Hutchins said that initial milestone dates are in place, but cited OIF policy in not sharing them. However, he said that such IAs typically take two years to reach final publication.

Finally the MLG IA project will focus on specifying new functionality to 4 x 25-Gbps applications such as 100-Gigabit Ethernet. The goal is establishment of a 10:4 mux MLG function to convert up to 10 independent 10-Gbps links into 4 x 25-Gbps, with a complementary 4:10 demux function at the receive end. Huchins said that current gearbox technology doesn’t enable the 10-Gbps links that feed the gearbox to maintain their individual identities after they’re multiplexed. The MLG Project will aim to define in-band coding that preserves 10GBASE-R physical lane-to-lane ordering and in-lane bit ordering to support synchronous and asynchronous 10G lanes.


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