Tektronix, Inc. has introduced new optical modules for the DSA8300 Digital Signal Analyzer sampling oscilloscope that support optical compliance testing of Ethernet at speeds up to 100 Gbps.
The new modules create a single mainframe for optical compliance test for Ethernet at speeds of 10G, 40G, and 100G (4x25) with up to 4X the throughput compared to alternative products on the market, superior native jitter, and an integrated clock recovery capability, the company claims. The complete toolset eliminates the need for additional test equipment such as optical-to-electric converters.
In addition, Tektronix is offering an updated jitter analysis feature with what the company claims is the industry's only bounded uncorrelated jitter (BUJ) separation techniques for better identification of crosstalk issues.
The DSA8300 Digital Serial Analyzer is a modular system designed to provide excellent bandwidth and signal fidelity, high-performance TDR and interconnect analysis, and accurate analysis of signal impairments for current and emerging data communications technologies, the company says. With six module slots, the DSA8300 can simultaneously accommodate a clock recovery instrument, a precision phase reference module, and multiple electric and optical acquisition modules to provide a broad range of test configurations in one instrument. With all of the capability in one instrument, engineers can free up more space on their lab benches, reduce calibration expense, and interact with a single, familiar user interface.
"Engineers want a single test instrument for critical optical measurements," said Brian Reich, general manager, performance oscilloscopes, Tektronix. "This instrument set covers test support for all of the critical IEEE802.3 and Fibre Channel standards. And by providing the industry's first sampling oscilloscope solution with BUJ analysis, we are helping to address crosstalk test challenges faced by our customers on these higher data rates."
The latest version of the IEEE Ethernet Optical and Electrical standards at 40 and 100 Gbps are 4-lane and 10-lane architectures. In the multi-lane architecture, a critical design challenge is to accurately identify lane-adjacent crosstalk, which typically shows up as BUJ. Until now, traditional jitter separation techniques like Dual-Dirac did not account for the non-periodic part of BUJ, and instead erroneously added it to random jitter, leading to inaccurate jitter estimates compared to results for a bit error ratio tester (BERT). The new capability for the DSA8300 ensures that crosstalk signal issues are measured and accounted for properly and accurately.
The DSA8300, with supporting optical modules and updated toolset with BUJ support, is available now worldwide. Pricing for the DSA8300 Mainframes starts at $27,500 US MSRP and the Optical Sampling Modules begins at $31,500 US MSRP.
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