TeraSquare unveils low-power 100G parallel CDR technology at ECOC

Fabless semiconductor developer TeraSquare Inc. of Korea says it will demonstrate its parallel clock data recovery (CDR) integrated circuit (IC) at ECOC 2013 later this month. The company claims the chip will dramatically improve signal quality across 100G systems and deliver massive savings in power consumption.

TeraSquare assrts that its parallel CDR, the TS-CM44013, slashes IC power consumption to 0.75 W compared to average CFP4/QSFP28 levels of 3.5 W, does not require a clock reference, and has built in jitter tolerance (JTOL) testability – avoiding the need for external test and measurement equipment.

“Our new IC is truly revolutionary,” claimed TeraSquare’s CTO, Dr. Jinho Park. “It is, by a considerable margin, the lowest power solution the market has ever seen, and this critical requirement is just one of the major features that we believe will make our new development so significant.”

TeraSquare’s 100-Gbps parallel CDR supports 25.0–28.3 Gbps per lane in an 8x8-mm standard BGA package for CFP4/QSFP28 optical transceiver modules and supports CEI-28G-VSR interface specifications. The device features a reference-less mode and jitter filtering operation with no external filter capacitor required, TeraSquare asserts. The IC also includes on-chip test functions, including JTOL and PRBS generator, all of which will be demonstrated at TeraSquare’s stand at ECOC.

TeraSquare will also be introducing its second product at ECOC, a 10x10-Gbps and 4x25-Gbps 100G reverse gearbox CDR fully supporting OIF MLG1.0/MLG2.0 and CEI-28G-VSR standards for CFP4/QSFP28 modules. This product has all the features of TeraSquare’s 100G parallel CDR and consumes 1.1 W of power. First samples will be available in February 2014.

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