Semiconductor intellectual property (IP) supplier Open-Silicon has unveiled additions to its line that bring the company more directly into the Ethernet space. The IP products address Ethernet Physical Coding Sublayer (PCS), Flex Ethernet (FlexE), and multi-channel, multi-rate forward error correction (FEC) requirements within Ethernet endpoint and Ethernet transport applications.
Open-Silicon says the Ethernet PCS IP is compatible with different MII interfaces for MAC connections, working with off-the-shelf MAC and SerDes devices. The IP supports 64b/66b encoding/decoding for transmit and receive, as well as data rates from 10 to 400 Gbps. It complies with IEEE 802.3 and supports Ethernet and Flex Ethernet.
The FlexE IP supports Ethernet MAC rates from 10 to 400 Gbps and is designed to work with off-the-shelf MACs. The FlexE IP conforms to the Optical Internetworking Forum (OIF) Flex Ethernet standard 1.0; it supports FlexE aware, FlexE unaware, and FlexE terminate modes of mapping over the transport network, the company says.
The FEC IP is designed to enable 56-Gbps PAM4 SerDes integration. The company says its single-instance IP is compatible with off-the-shelf SerDes and supports bandwidths up to 400 Gbps with the ability to connect 32 SerDes lanes. It also supports the Interlaken and Ethernet standards.
The new IP joins Open-Silicon's eighth-generation Interlaken IP, which the company says supports up to 1.2-Tbps performance and up to 56-Gbps SerDes rates. The IP networking subsystem is available now for ASIC design starts, either as a licensable IP subsystem or individual IP cores.
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