The organizers of the Optical Fiber Communications Conference (OFC) have revealed details of a presentation that will describe an approach to chip-to-chip communications based on silicon photonics. The paper will detail the development of a modulator and a tunable filter created using IBM’s CMOS process that the paper’s presenters believe could make inter-chip communications 10X more energy efficient than current electronic approaches.
Paper Tu2E.7, titled “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” is the work of researchers at the University of Colorado, Boulder; the Massachusetts Institute of Technology (MIT); and the University of California, Berkeley. The project is part of the U.S. Defense Advanced Research Projects Agency’s (DARPA’s) Photonically Optimized Embedded Microprocessors (POEM) project.
The researchers envision the devices being used in interconnect applications such as that between a central processing unit and its memory. While research into optical means of chip-to-chip communications isn’t new, most of these efforts have focused on using conventional optical materials or specialized processes that result in either bulky packages or difficulty in commercialization. The use of CMOS processes would overcome both drawbacks.
"As far as we know, we're the first ones to get silicon photonics natively integrated into an advanced CMOS process and to achieve energy efficiencies that are very competitive with electronics," said Mark Wade of the University of Colorado, Boulder, who will present the paper Tuesday, March 11, at 3:30 PM in Room 123 of the Moscone Center in San Francisco.
Wade envisions the approaches investigated within the POEM project as a springboard to multiple applications for silicon photonics. "This is a really nice first step for silicon photonics to take over some areas of technology where electronics has really dominated and to start building complex electronic/photonic systems that require dense integration," he said.
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