Avago Technologies (NASDAQ:AVGO) says it has demonstrated what it asserts is the first 56-Gbps pulse-amplitude modulation (PAM)4 serializer/deserializer (SerDes) across copper backplanes and optical interconnects. The company says it already has customers designing ASICs in 28-nm and 16FF+ process technologies using its PAM4 SerDes cores.
The company sees the technology as applicable to a wide range of applications, including chip-to-chip, chip-to-module, low-cost direct-attached cable, and copper backplanes down to 35-dB loss, as well as in support of next-generation switches and routers. The SerDes supports speeds from 1 Gbps to 56 Gbps, including existing 10G/25G/40G/50G/100G Ethernet, Fibre Channel, and OIF CEI NRZ speeds. The technology potentially could be applicable to future 400 Gigabit Ethernet applications, as the P802.3bs Task Force is considering 50-Gbps electrical and optical lanes as part of the specifications (see "400 Gigabit Ethernet Task Force ready to get to work").
The company says the demonstrations show the 56-Gbps PAM4 SerDes running PRBS31 traffic, error-free, across various interconnects. It is now available in silicon, Avago adds.
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