31 July 2003 San Jose, CA Lightwave -- Cypress Semiconductor Corp. and Xilinx Inc. have announced the collaborative co-development of reference designs for next-generation communications and memory products. The first product resulting from the newly formed relationship is a reference design for implementing a complete "Fiber-to-Fiber" data over SONET/SDH solution. Further designs targeting packet-processing applications are currently in development by the two companies.
The design--which uses transparent generic framing procedure (GFP-T) for data encapsulation and virtual concatenation for optimal bandwidth utilization--deploys two client channels over SONET, each independently configurable for multi-protocol standards, including any combination of Gigabit Ethernet (GbE), Fibre Channel, Enterprise Systems Connection (ESCON), and Fibre Connectivity (FICON).
By leveraging Cypress's MetroLink2T-2 core to implement GFP-T functions, the reference design is optimized for the Xilinx Virtex-II FPGA. According to Cypress, its MetroLink core is the first Link Layer Device (LLD) on the market to offer GFP-T. The Virtex-II device uses flexible SelectI/O-Ultra technology to seamlessly interface to Cypress's POSIC2GVC SONET/SDH framer and HOTLink II serializer/deserializer (SERDES).
"Using the Virtex-II device to implement the MetroLink2T-2 link-layer function enabled us to provide our customers with a complete metro-transport solution quickly and with little risk as their requirements evolve throughout the design cycle," said Geoff Charubin, director of marketing for Cypress's Data Communications Division. "Using this reference design, Multi-Service Provisioning Platform (MSPP) and dense wavelength division multiplexing (DWDM) manufacturers can quickly bring a GFP-T platform to market, allowing their system architects to focus on higher-layer functions within their system and differentiating their solution vs. the competition."
"We are pleased to work with Cypress to further demonstrate the capability of our Virtex-II FPGAs in advanced packet processing solutions," said Jerry Banks, director of Partnerships and Alliance marketing at Xilinx. "This joint reference platform includes the Cypress MetroLink LLD core implemented on the Xilinx Virtex-II FPGA and enables communication system designers to bring 'SONET over any protocol' to market more quickly."
As part of the interoperability testing, critical interface timing between the POSIC2GVC framer, the HOTLink II SERDES, and the FPGA have been completed and verified; a complete reference design with application note, including Verilog and VHDL code, is included to speed time-to-market. Cypress's participation in the Xilinx Reference Design Alliance Program means the companies will jointly market the reference design board, cross-reference their application notes and product data sheets on each other's web sites, and provide layout guidelines and board schematics. For more information on the reference design, visit www.xilinx.com/company/reference_design/cypress.htm.