24 April 2003 Sunnyvale, CA Lightwave -- Fujitsu Microelectronics America introduced a System Packet Interface Level-4 (SPI-4) I/O macro, providing point-to-point connectivity between physical layer and link layer devices in network designs.
The new SPI-4 macro is compliant with OIF SPI4-02.0, phase 2 standard, and supports bandwidths for OC-192, 10 Gigabit Ethernet and packet over SONET applications, along with multiplexing/demultiplexing, and bridging functions. It is fabricated in both Fujitsu's advanced 0.11-micron and 0.18-micron CMOS process. The 0.11-micron version uses supply voltages of 1.2V and 2.5V while the 0.18-micron version uses supply voltages of 1.8V and 3.3V. This macro is available now and been applied in a variety of complex ASIC designs.
The new SPI-4 joins Fujitsu's family of high-speed interface macros for optical long haul, metro area network and enterprise applications. This series includes XAUI-compliant 3.125-Gbit/sec transceivers, OC-48 compliant 2/4/8/16-channel 3.125-Gbit/sec transceivers, an OIF compliant 16-channel SFI-4 (SERDES Framer Interface-4) macro and the OIF compliant 16-channel SFI-5 macro. These macros are designed using an advanced 0.11-micron and 0.18-micron process, with proven reliability and manufacturability. All are supported by high-performance ASIC libraries that include dense memory macros, along with a variety of state-of-the-art flip-chip packages. Fujitsu provides full support for all the high-speed I/O macros, together with Verilog and design compiler models and library exchange format for floor planning.
"High-performance applications will be one of the strongest areas in the ASIC industry, and the companies that can meet the demands of these high-end opportunities will be well-positioned," said Jordan Selburn, principal analyst of application specific semiconductors and PLDs at iSuppli Corporation. "Standards compliance also will be essential to meet the needs of the segment," he added.