PMC-Sierra demos 6.25-Gbit SERDES technology and evaluation platform

3 February 2004 Santa Clara, CA Lightwave -- PMC-Sierra, Inc. has unveiled the PM8359 QuadPHY 6G SERDES transceiver technology and evaluation platform at Molex, Inc.'s booth at DesignCon. The company touts the CMOS-based QuadPHY 6G as the industry's first multi-gigabit serial backplane transceiver to be compliant with the Optical Internetworking Forum's (OIF) 6-Gbit/sec long-reach specification.

Feb 3rd, 2004

3 February 2004 Santa Clara, CA Lightwave -- PMC-Sierra, Inc. has unveiled the PM8359 QuadPHY 6G SERDES transceiver technology and evaluation platform at Molex, Inc.'s booth at DesignCon. The company touts the CMOS-based QuadPHY 6G as the industry's first multi-gigabit serial backplane transceiver to be compliant with the Optical Internetworking Forum's (OIF) 6-Gbit/sec long-reach specification.

The OIF Common Electrical I/O (CEI) 6+ Long Reach specification (Draft 4.0) defines the requirements for driving gigabit-serial signals across a backplane at extended distances and at higher data rates.

"The OIF, recognizing the market acceptance of the High Speed Backplane Initiative (HSBI) mission to support legacy backplanes, realized that specifications for 6+Gbit/sec electrical signaling were necessary. Its industry importance and commercial implications are being recognized by our membership, as shown by PMC-Sierra's announcement," said Steve Joiner, OIF technical committee chair.

"PMC-Sierra's QuadPHY 6G enables customers to upgrade their current backplanes to support higher data rates while maintaining backward compatibility with installed line cards," said Mark Stibitz, vice president and general manager of PMC-Sierra's Enterprise Storage Division.

The QuadPHY 6G multiplexes and demultiplexes eight 3.125-Gbit/sec serial links into four 6.25-Gbit/sec serial links. To achieve system reliability at these speeds, design focus on bit-error-rate performance is required. An adaptive decision feedback equalization (DFE) design ensures robust serial link operation designed for a bit-error rate as low as 10E-18.

The adaptive DFE enables the QuadPHY 6G to deploy industry-standard NRZ binary signaling at 6.25 Gbits/sec. With half-rate and quarter-rate operation modes, the QuadPHY 6G provides electrical signaling as well as rate compatibility to connect to legacy line cards.

Engineering samples of the QuadPHY 6G SERDES are available now and priced at $250. The QuadPHY 6G is designed with 0.13-micron CMOS technology and packaged in a 19x19-mm 320-pin flip chip ball grid array (FCBGA) assembly. The design support package includes an evaluation kit, board layout and design documentation, VHDL source code, configuration scripts, application notes and user manual. The QuadPHY 6G evaluation kit is priced at $4,900 per unit and is available today.

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