Zarlink introduces analog timing chip for OC-12 optical line cards
25 November 2003 Ottawa, Canada Lightwave -- Zarlink Semiconductor today launched an analog timing chip for SONET/SDH line cards operating at up to OC-12/STM-4 rates. The ZL30415 analog phase locked-loop (PLL) is an integrated timing device that offers jitter performance surpassing industry requirements and a frequency-selectable output clock that reduces design costs.
25 November 2003 Ottawa, Canada Lightwave -- Zarlink Semiconductor today launched an analog timing chip for SONET/SDH line cards operating at up to OC-12/STM-4 rates. The ZL30415 analog phase locked-loop (PLL) is an integrated timing device that offers jitter performance surpassing industry requirements and a frequency-selectable output clock that reduces design costs. Most timing chips do not match the ZL30415 device for value, delivering marginal jitter performance or lacking the features necessary to meet OC-12 requirements.
The ZL30415 timing chip provides ultra-low jitter performance of a maximum of 3.3 psec rms (root mean square) for OC-3/STM-1 rates, and 3.5 psec rms for OC-12/STM-4 applications. This performance surpasses Telcordia's GR-253-CORE requirements for OC-3 to OC-12 optical rates, and the International Telecommunications Union-Telecommunications G.813 Option 1 and 2 specifications for STM-1 to STM-4. Zarlink's analog PLL is one of the few available devices meeting the more stringent jitter limits imposed by framers and other interfacing devices.
Offering analog, digital and module timing devices, coupled with reference designs and engineering support, Zarlink is the only company with end-to-end timing and synchronization products for SONET/SDH equipment.
Analog PLLs perform timing and network synchronization functions in line cards, regenerating and multiplying clock signals to higher frequencies, and cleaning up jitter, a short-term variation in clock timing that causes data errors in optical equipment.
The ZL30415 timing chip provides two output clocks one fixed 19.44 MHz CMOS clock, and a frequency- selectable LVPECL (low voltage positive emitter coupled logic) clock. Designers may select any of the standard frequencies used in OC-3/STM-1 to OC-12/STM-4 applications 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or 622.08 MHz.
The frequency-selectable output clock simplifies the design of OC-3/OC-12 line cards. For example, designers using the ZL30415 device in a system with both OC-3 and OC-12 line cards requiring different LVPECL clock outputs can simply cut and paste the design from one line card to the other, changing only the programmable output frequency required for the given application.
The LVPECL clock output interfaces directly with other devices on SONET/SDH line cards, such as framers, mappers, and SERDES (serializer/deserializer) chips, thus eliminating the need for external translation circuitry that adds cost, consumes power and increases the design footprint.
The ZL30415 device can be used on its own to address timing requirements for line cards operating at up to OC-12/STM-4 rates, or in combination with Zarlink digital PLLs such as the MT9046 or ZL30410 devices, in highly featured timing systems.
The ZL30415 timing chip enhances Zarlink's portfolio of analog PLLs with different features to meet synchronization and jitter requirements for SONET/SDH line cards in network core, metro, edge and access equipment operating at OC-3/STM-1 to OC-192/STM-64 rates.
Availability, packaging, and price
The ZL30415 analog PLL is in volume production. The chip is offered in a 64-ball CABGA (chip ball grid array) measuring 8 mm x 8 mm. In quantities of 1,000, the ZL30415 device is priced at $24 (US).