Low-power serializer with clock synthesis

Nov. 7, 2001--Maxim Integrated Products has announced the MAX3892 3.3 V, 2.5-Gbit/sec and 2.7-Gbits/sec 4:1 serializer with clock synthesis and LVDS inputs.

Nov 7th, 2001

Maxim Integrated Products has announced the MAX3892 3.3 V, 2.5-Gbit/sec and 2.7-Gbits/sec 4:1 serializer with clock synthesis and LVDS inputs. The MAX3892 is ideal for converting 4-bit-wide, 622-Mbits/sec parallel data to 2.5Gbits/sec serial data in DWDM and SDH/SONET applications. It forms a complete two-chip 2.5-Gbits/sec and 2.7 Gbits/sec transceiver solution when used with the MAX3882 1:4 deserializer with clock recovery.

Operating from a single 3.3-V supply, the MAX3892 accepts 622-Mbits/sec LVDS parallel data inputs and delivers differential CML serial data and clock outputs while consuming only 455 mW of power, claims the company. A 4-bit x 4-bit FIFO allows for any static delay between the parallel input clock and the internally synthesized clock. Delay variation up to a unit interval is allowed over temperature. A fully integrated PLL synthesizes an internal 2.5-GHz serial clock from a 622.08-MHz, 155.52-MHz, 77.76-MHz, or 38.88-MHz reference clock. A loopback data output is provided to facilitate system diagnostic testing.

The MAX3892 is available in a 44-pin QFN package over the extended temperature range (-40 degrees Celsius to +85 degrees Celsius), and is priced at $31.63 (in quantities of 1,000). Evaluation kits are available.

For more information, visit the company's Web site at www.maxim-ic.com.

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