July 24, 2006 Sunnyvale, CA -- Applied Micro Circuits Corp. (AMCC) today introduced the S19256, a 10-Gbit/sec dual Clock Data Recovery (CDR) device designed for use in short reach and intermediate reach XFP modules. The S19256 is based on the company's existing S19233 dual CDR, offering customers a high-performance solution with a modified feature set for reduced power, say company representatives.
The S19256 features a small footprint (6x6 mm2), compatible with the S19233 and targets short reach (2 km) and intermediate reach (40 km) applications for 10-Gbit/sec data transmission for multiple standards, including 10-Gigabit Ethernet (10-GbE), SONET/SDH, or Fibre Channel. The S19256 device is equipped with a built-in equalizer to mitigate data-dependent jitter generated during the transmission of signals in FR-4 material. Customers benefit from this ability to compensate for any deterministic jitter by realizing overall improved system jitter performance, say AMCC representatives.
The S19256 provides high cross talk isolation and can be seamlessly connected on the motherboard to AMCC's 10G Serdes devices, including the S19235 or S19237. AMCC's dual CDR portfolio offers designers a single pin-compatible family with optimized feature sets that target different reach and price points for various XFP applications. The S19256 is one-third less expensive than the EDC-based long-reach S19233 offering, say company representatives.
"Customers are pleased to see this broadening in AMCC's PHY product offerings to meet the growing need for a lower-power, low cost 10-Gigabit Ethernet optical module," reports Sam Fuller, vice president of marketing at AMCC. "The 19233 and 19256 products from AMCC provide a common footprint for both the short-reach and long-reach markets. Most of our customers are offering products for both markets but face different market demands in performance and price. The common design platform of the S19256 and S19233 enables our customers to offer optimized solutions in both markets based on a common product family," he adds.
The optical receiver of the S19256 integrates an AGC amplifier with offset cancellation circuitry with the CDR function. The transmit electrical side of this device also has an equalization circuit and CDR that reshapes the data after up to 20" of transmission over copper on FR-4 PWB material, with low jitter generation of 25 mUI. The low-jitter CML interface is designed to be compliant with the bit error rate requirements of the Telcordia and ITU-T standards.
Packaged in a 6x6 mm2 49-pin PBGA, 0.8-mm pitch, the S19256 is currently sampling. Volume production is scheduled for the fourth quarter of 2006. The S19256 is available in both leaded and full RoHS-compliant packages.