Zarlink chip meets exacting standards for high-performance optical clocks
January 21, 2002--Zarlink Semiconductor today announced that it has designed what it claims is the world's first commercial digital PLL (phase locked loop) chip that fully meets rigorous international standards for very high performance synchronization in SONET/SDH systems.
Zarlink Semiconductor today announced that it has designed what it claims is the world's first commercial digital PLL (phase locked loop) chip that fully meets rigorous international standards for very high performance synchronization in SONET/SDH systems.
Zarlink's newest PLL is based on a patent-pending architecture that incorporates three independent PLLs within a single chip. This approach enables the device to reduce signal wander--a cyclical variation in signal frequency that is a prime cause of data errors in optical communications networks--to levels stipulated by international standards.
As a result, the chip is the industry's first off-the-shelf SONET/SDH digital PLL to fully meet the exacting synchronization requirements of Telcordia's GR-1244-CORE and GR-253-CORE standards for SONET Stratum 3E clocks, and the ITU's G.812 requirements for SDH Type I clocks. The chip also provides multiple clocks for legacy PDH (plesiochronous digital hierarchy) equipment, and generates timing for CompactPCI, ST-BUS and GCI backplanes.
Zarlink's new device is a network element PLL that provides synchronization in SONET and SDH systems. The chip can be used on timing cards and line cards in SONET/SDH add/drop multiplexers and uplinks, terminal multiplexers, integrated access devices, and ATM edge switches.
It chip architecture has enabled Zarlink to meet key technical challenges in designing a digital PLL for SONET Stratum 3E and SDH Type I clocks--controlling signal wander and timing transients, and providing holdover accuracy. For example, the device's holdover accuracy of 0.1 ppb (parts per billion) permits network equipment to continue to transmit and receive data with a high degree of accuracy, even when the source of network synchronization is disrupted or changed, explain company representatives.
The device will begin sampling in April 2002 and is the second in Zarlink's family of high-performance SONET/SDH digital PLLs.
For more information about Zarlink Semiconductor (Ottawa, Canada), visit the company's Web site at www.zarlink.com.