Zarlink delivers digital timing chip for OC-3 line cards, jitter performance 30% better than competing products

29 July 2003 Ottawa, Canada Lightwave--Zarlink Semiconductor today expanded its portfolio of timing devices for optical networking equipment with the ZL 30410 digital PLL (phase-locked loop), a full-featured timing chip with the industry's lowest jitter, for access line cards operating at OC-3 rates.

Jul 29th, 2003

29 July 2003 Ottawa, Canada Lightwave--Zarlink Semiconductor today expanded its portfolio of timing devices for optical networking equipment with the ZL 30410 digital PLL (phase-locked loop), a full-featured timing chip with the industry's lowest jitter, for access line cards operating at OC-3 rates.

With the ZL30410 digital PLL and the company's analog PLLs for line cards, Zarlink is the first semiconductor company to offer both digital and analog timing devices for standards-compliant line cards in high-speed SONET/SDH access systems.

Zarlink's ZL30410 timing chip generates and synchronizes clock signals used by other line card devices, such as OC-3/STM-1 framers, mappers, switches, and optical line interface chips. The company's analog PLLs connect seamlessly to the ZL30410, and support higher-speed applications by producing clock signals for OC-12/STM-4 or OC- 48/STM-16 framers.

"To handle rising traffic volumes at the network edge, access systems must operate at higher speeds, and that makes their timing circuitry more complex," said Michael Rupert, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "Our digital and analog line card PLLs are fully tested for interoperability, which reduces complexity and makes it easier for designers to comply with stringent SONET/SDH network timing standards."

Several global equipment vendors are evaluating Zarlink's line card chips for use in routers, multi-service access devices, digital subscriber line access multiplexers, gateways, and next-generation digital loop carriers.

The jitter performance of the ZL30410 chip is best-in-class, with ratings 30% lower than comparable digital PLLs, according to the company. Jitter, a cyclical variation in signal frequency, causes data errors in optical networks. The superior performance of Zarlink's chip means it can generate - without external components- the 155.52-MHz clocks that drive OC-3/STM-1 access uplinks, and the 16.384-MHz clocks that drive jitter-sensitive TDM digital switches. By contrast, clocks at these frequencies produced by digital line card chips from other vendors must be "cleaned" of jitter by external analog PLLs.

In addition to clocks for OC-3/STM-1 links, Zarlink's ZL30410 chip generates all other clocks typically used in high-speed access line cards, including a 19.44 MHz clock, and clocks for services delivered over ST-BUS, DS1/E1, DS2, and DS3/E3.

On its inputs, the ZL30410 accepts two reference clocks. It detects the frequency of both clocks and synchronizes to any combination of 8 KHz, 1.544 MHz, 2.048 MHz, and 19.44 MHz.

The ZL30410 chip offers "hitless" reference switching, a feature that enhances reliability and eases maintenance procedures. The device continuously monitors both input references. If the active reference is interrupted, the chip switches instantly to holdover mode, generating its own reference clock based on data collected from past reference signals. This gives the system time to react to the problem, and if required, switch the ZL30410 chip to its other input reference signal without disturbing its output clocks.

The chip complies with Telcordia's GR-253-CORE for OC-3 jitter generation, and the International Telecommunication Union-Telecommunications' G.813 Option1 for STM-1 jitter generation. It is also compatible with GR-253-CORE SONET Stratum 3 clocks, and G.813 SEC (slave equipment clocks).

The ZL30410 digital PLL is in production. The device is offered in an 80- pin low quad flat pack package measuring 14x14 mm. In quantities of 1K, the chip is priced at US$22.50 each.

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