The year ahead will mark the transition of DOCSIS 3.1 from the planning to the execution stages. The ascendance of DOCSIS 3.1 will be marked by an increasing number of announcements. The standard is finished, and chip makers, equipment vendors - working with CableLabs and MSOs - are busy finalizing the equipment that will enable field trials and eventual rollouts.
The Consumer Electronics Show in Las Vegas last week is a good barometer of the where things stand. However, the industry got a head start with a late 2014 interoperability “plugfest” event at CableLabs. Not too much information was released by the organization. Six companies participated. Three of the six are known: Cisco, Averna and STMicroelectronics have confirmed their participation.
CableLabs’ President and CEO Phil McKinney said there will be interop events throughout the year. It is less certain when the certification process will begin. This is a more formal, longer and more intense process aimed at ensuring that products fully comply with the specification and can be deemed DOCSIS 3.1 compliant. The bottom line is that the specification, which was introduced in October 2013, is closing in on completion - and at a speed that perhaps is unprecedented.
McKinney is happy with the progress and echoed comments that he had made late last year. “From my perspective, we are ahead of schedule and fully on track for devices to be ready by the later half of this year and for field trials in early 2016.”
Most of the world knows that it is the new year because they watch the ball drop in Times Square in New York City. Folks in the consumer electronics and related industries know because they are headed to the Consumer Electronics Show in Las Vegas. At the show, several companies made DOCSIS 3.1-related announcements or showed what they are working on.
Broadcom:The company used CES to introduce what Jay Kirchoff, the company's vice president of marketing for the North American Connectivity Group, said is the industry’s first system on a chip (SoC) for DOCSIS 3.1. SoCs - squeezing all the functionality into one piece of silicon - reduce power and space requirements, Kirchoff said. Possible conflicts between chips from different vendors also are eliminated, he said. The fewer the chips, the greater the efficiency and overall simplicity of the product.
The BCM3390 is a reference design that initially will be used in modems. Gateways and other configurations will follow. The BCM3390 is capable of 5 Gbps in the distribution network and 2 or 3 Gbps in the last mile. The WiFi speeds can reach 2 Gbps, Kirchoff said.
Kirchoff said that Broadcom demonstrated two-way traffic at CES, but that not all the functionality of the chipset was on display. He said the chips came from the fab shop only six weeks before the show, and there was not enough time to validate that everything is working. He said Broadcom plans to enter the BCM3390 in CableLabs’ first certification wave.
MACOM:MACOM introduced a line of passive devices for DOCSIS 3.1 that extend the upstream frequency by as much as 300 MHz, said Alan Miller, the company’s product manager for carrier networks. He added that the passives’ downstream capabilities also are expanded to match the new DOCSIS 3.1 requirements. Miller said the passives are being designed to be used in nodes, to line extenders and inside homes.
STMicroelectronics(NYSE:STM): Ismail Allalcha, STMicrosystems' strategy and ecosystem marketing manager, said the company's new chipset - which has not officially been named - is aimed at gateways and potentially modems. He was constrained in what he could say about the emerging product, which still is under development.
Allalcha said there are minimal differences between the MAC layers in DOCSIS 3.0 and 3.1. The significant differences - and the challenge for chip makers - is in the PHY layer, which is the lowest level in the OSI model. He said the challenge lay in the increased amount of data and the transition from quadrature amplitude modulation (QAM) to orthogonal frequency division multiplexing (OFDM).
The chipset has not yet been integrated into a SoC. Allalcha said that it will be at some time in near future.