New SONET era spurs framer/mapper usage

As the telecommunications industry slowly pulls itself out of acute depression, a major emerging issue will be what the next generation of infrastructure will look like. While we should always expect the unexpected—networking technology will no doubt take some surprising turns in the next few years—it is already clear that SONET/SDH will play a much bigger role than anyone might have expected during the optical boom era.

Ubiquitous all-optical WDM rings—the objective of many a product development program of a few years back—now seem more like futuristic dreams than the kind of thing a network planner would spend much of her time thinking about. Ethernet's push into the public carrier networks, which once seemed so certain, is more likely to occur in the form of Ethernet traffic growth over a SONET/SDH infrastructure than as Ethernet replacing that infrastructure. The boom era forecasts for the cost/performance advantages of Ethernet have proved illusory and the institutional commitment of the incumbent carriers to SONET/SDH has proved hard to break.

CIR's research suggests that the future of telecom infrastructure deployment over the next five years will look much like what was going on before the optical bubble. Put simply, there will be more SONET/SDH systems put in place (with OC-192 much to the fore) and lots of different traffic types flowing over it. Adjusting to these new realities will not be easy for components and systems vendors born in the all-optical boom era. But like all new twists and turns in the marketplace, these new realities will create new opportunities and a need for understanding how those new opportunities can be tapped.

CIR researchers believe that current trends point to new potential for the business of making and selling framers and mappers that are key to the electronics behind SONET/SDH networks. Framers take the data from the SONET/SDH physical layer chips and process the overhead. They then pass the data to the mappers, which then map data that is not intrinsically SONET/SDH in nature onto the SONET/SDH carrier. In a telecom environment that stubbornly refuses to move to a single type of traffic in spite of some of the more optimistic visions of analysts, mappers have a particularly important role to play.

The SONET/SDH mapping and framing business has attracted some of biggest names in communications chips (Agere Systems, Agilent Technologies, AMCC, Cypress Semiconductor, Infineon, Intel, PMC-Sierra, TranSwitch, and Vitesse Semiconductor) as well as more specialist companies (Ample, Crimson Microsystems, Galazar, Mindspeed, and Multilink.) All these companies compete on the benefits of specific approaches to integration, levels of power usage and of course features. A key innovation has been the incorporation of generic framing procedure (GFP), which provides for virtually any kind of traffic to be mapped onto SONET/SDH.

Along with aiding the transport of multiple services, GFP also supplies virtual concatenation, which provides for better bandwidth efficiency. With so much capacity these days, better bandwidth utilization is probably not the primary concern of carriers or equipment vendors, but it may be in the future.

Obviously, to be of competitive advantage to chip makers, framers and mappers must be designed with more than just GFP—or indeed anything specifically designated as generic! As a way of distinguishing themselves in the marketplace, framer and chip makers are also likely to be looking to the latest improvements in semiconductor manufacturing processes and materials, along with innovations in chip design (e.g., the systems-on-a-chip approach).

However, our discussions with semiconductor manufacturers, equipment vendors, and services providers all suggest that the most immediate way makers of framers and mappers can meet the needs of the marketplace is to demonstrate their products can make a significant contribution to telecom gear becoming a lot less expensive and a lot more compact. That is vital in a world in which carrier capital expenditures are expected to recover only slowly in 2004 and where much of the economic activity is likely to be centered on the cost-sensitive, real estate-challenged metro and access segments.

At the chip level, these concerns feed into the need for integration of more functionality into a single device. Notable trends in this area include the following:

• Advanced error checking techniques—particularly forward error correction—are being integrated onto framers. Formerly, these techniques have been embodied in separate chips. However, for some high-end long-haul gear, error-checking may assume sufficient purpose to require its own co-processor.
• Integration of framers and mappers onto a single chip makes increasing sense, since the traditional distinction between these two kinds of functionality reflects to some extent the large-scale integration (LSI) capabilities of a decade ago. The steady progress of Moore's Law has also enabled other kinds of SONET/SDH functionality to be built onto the chip. Crossconnect capability is the obvious choice here. Even low-end SONET/SDH boxes have some crossconnect capability now. Gradually, or perhaps not so gradually, all the functionality related to aggregation, grooming, and transport of data is going to find its way onto the same chip.
• Integration of control-plane and potentially data-plane processing onto the same chip with the data transport functionality is an emerging trend. This approach is now being attempted to a limited degree. The advantages are those always associated with the LSI of any necessary functionality, but as reported by customers, there are some real downsides. Framer/mapper/processor combos are likely to be priced well over the budget of customers looking only for framing and mapping capabilities. Customers have not always bought communications processors and framers/mappers from the same company. Commitment to a particular processor also implies certain software choices, so suddenly the choice of framer or mapper becomes a much bigger decision for the customer, complicating the marketing and sales process for the chip maker.

That, of course, raises the age-old problem of compatibility between products from chip manufacturers. Some chip companies have agreed to get over this problem and the Optical Internetworking Forum is also doing some work in this field. For example, it has published Implementation Agreements that enable framer and switch components from multiple vendors to interoperate. These agreements address such matters as integrity monitoring and connection management where incompatibilities can arise.

But integration is certainly not the only way to meet the performance requirements of the current framer/mapper market. Some manufacturers are looking to design issues like improved jitter attenuation as well as other factors that enable the use of lower-cost line interface units and boost performance. In some cases the marketing strategy at play here is clearly intended to get the customer to spend more on a particular manufacturers' framer /mapper while promising the customer savings from not having to buy another manufacturer's component—a win/win situation for the framer/mapper product. Another way to distinguish framer/ mapper products is to reduce power consumption, which is often an area of major concern to equipment manufacturers and does not get the prominence it deserves.

The majority of equipment vendors are probably not entirely ready to buy the framing and mapping and the switching and processing all squeezed together on a single chip and from a single source. So the more mundane issues of design and power consumption will continue to be of key importance.

Lawrence Gasman is president of CIR (Charlottesville, VA), a market research and industry analysis firm covering the telecommunications and optoelectronics business. He can be reached at [email protected]. Research for this article is based on CIR's continuing coverage of the transmission components and communications processor market.