Passive optical networks (PONs) deliver as much bandwidth as VDSL or more, and over much longer reaches, providing an excellent alternative for high-speed broadband services. But PON deployment has been slowed by the high cost and complexity of chipsets.
As the PON market grows, vendors are investing in developing chips with greater integration. This integration, along with economies of scale, will lower the per-port price of PON equipment and therefore encourage growth in this technology.
As more optical line terminals (OLTs) are built with IP/MPLS uplinks, vendors seek to simplify their designs and reduce costs by using an Ethernet backplane. This allows OEMs to use low-cost Ethernet switch chips on a trunk card instead of more expensive ATM-switch-based cards. To support the Ethernet backplane, PON chip vendors will offer xMII and GMII interfaces. For backward compatibility, DSL vendors will continue to offer the traditional Utopia Level 2 for ATM processors.
The prevalence of oversubscription in the access network makes per-flow traffic shaping a requirement in carrier equipment; otherwise, voice and video services cannot reliably be mixed with data delivery. Wire-speed classification and filtering are also required to support differentiated services. Together, these features enable triple-play services, levels of data bandwidth (e.g., gold/silver/bronze), and other services. To support multiple protocols and traffic management, PON components typically integrate CPUs along with hardware accelerators.
The first class of OLT chips for PON that we’ll consider here targets EPON deployments. These consist of a PON controller, burst-mode transceivers, and optics. This chipset connects to an Ethernet switch chip, which links the OLT line card to an Ethernet (XAUI) backplane. Most of the first-generation solutions are optimized for a single PON port. The PON controllers integrate a sufficiently powerful CPU to perform interworking and manage the control path for a single PON connection. Consequently, the single-port line card does not need a network processor. A central trunk card aggregating the data from multiple line cards, however, may use a network processor for traffic management.
Compared with EPON controllers, GPON controllers increase the bandwidth and support more services. With a data rate of 2.5 Gbits/sec, GPON controllers need to support more Ethernet ports than EPON controllers do and therefore must scale up the performance of internal state machines and the CPU.
Because OEMs will develop multiport line cards, the next generation of PON components will be multiport devices. For example, these could include a four-port GPON controller with a SPI-4.2 interface to the network processor. In a multiport architecture, the PON controller is consumed by the transmission over the PON, and a separate network processor performs traffic management. The factors driving demand for multiport devices include lower cost, lower power dissipation, and denser line cards.
EPON vendors have used 0.18-µm technology to manage their development and manufacturing costs. These vendors can shrink their designs on 0.13-µm technology to reduce power dissipation and cost. Shrinking the design on 0.13-µm should allow PON vendors to develop multiport controllers. The more advanced technology is also needed for SPI-4.2 interfaces and faster CPUs.
Because of the mixed technology used in burst-mode transceivers, the transceivers are less likely to be integrated with the PON controller. Many of the PON vendors also rely on third parties for burst-mode transceivers. Because ODMs seek complete solutions, these PON-controller vendors will need to work closely with the transceiver vendors and, in some cases, develop bundling strategies.
Customer premises equipment (CPE) includes standalone modems and SOHO gateways. Compared with modems, gateways add capabilities such as firewall/NAT, wireless LAN, Ethernet switching, and voice interfaces. For at least the next year, PON will be sold primarily in modems. After that, PON, like DSL, will shift to integrated gateways, which will require more integrated processors.
With its early lead in deployments, EPON should lead the migration to a PON integrated processor. With its recent acquisition of Passave, PMC-Sierra is positioned to deliver the first integrated PON processors late this year. For GPON, the first step is the development of controllers for standalone modems in 2007. GPON-integrated processors will appear later, perhaps 2007 or beyond.
PON chipsets consist of an EPON/GPON controller, burst-mode transceivers, and optics. PON controller chips combine a CPU and hardware accelerators. Some vendors, like PMC/Passave, have integrated an ARM9 CPU, which provides headroom for gateway functions such as a web server and voice-over-IP processing. Although many processors support voice through external DSPs, products that integrate the voice-processing function reduce cost and power, gaining an advantage as packet voice grows in popularity.
Although PON controllers integrate packet memory to reduce external component count, they provide an external memory interface for applications that require additional packet storage. Because of the greater data rate, PON controllers provide xMII interfaces to connect with an external PHY or Ethernet switch for either Fast Ethernet or Gigabit Ethernet. PON controllers may integrate a Fast Ethernet PHY, because the technology is available from IP vendors, but they are unlikely to integrate the Gigabit Ethernet PHY in the near term, due to its greater cost and complexity.
In addition to the Ethernet ports, GPON controllers support TDM and ATM traffic. TDM requires an external codec, which is another mixed-signal chip likely to stay external to the controller. The different data types require bridging to the WAN, interworking among the protocols, and aggregation. This combination of functions requires more CPU performance than do DSL data pumps or EPON controllers.
The burst-mode transceivers and optics require mixed-signal technology and a different manufacturing process than for PON controllers. Consequently, these devices will not be integrated with controllers for the next few years. More likely, integration will result in a single device for all the transceiver functions, including the transimpedance amplifier, limiting amplifier, automatic gain control, and clock and data recovery.
Jag Bolaria (email@example.com) is a senior analyst at The Linley Group and author of “A Guide to Next-Generation Broadband” (see www.linleygroup.c