K-micro unveils OLT SerDes PHY for 10G EPON
MAY 11, 2009 -- New PHY is designed to meet the emerging IEEE802.3av standard developed by the 10GEPON task force, enabling symmetrical operation at 10.3125 Gbps for downstream and upstream links.
MAY 11, 2009 -- K-micro (Kawasaki Microelectronics America Inc.; search Lightwave for K-micro), a developer of advanced ASICs, has announced an optical line terminal (OLT) SerDes PHY for 10-Gbps Ethernet passive optical network (10G EPON) applications. Targeted to meet the emerging IEEE802.3av standard developed by the 10GEPON task force, the new PHY enables symmetrical operation at 10.3125 Gbps data for the downstream and upstream links.
"We are proud to be bringing a robust product for the 10GEPON market that meets the sub-50-ns lock time challenge, enabling development of OLT solutions without putting excessive demands on PMD devices," says Vijay Pathak, chief technology officer at K-micro. "Coexistence compatibility is retained by providing a bypass connection to an external 1.25-Gbps SerDes PHY for ONU [optical network unit] applications. SerDes IP will be available for ASIC integration in mid-2010 in 65-nm technology."
Using its burst-mode built-in self test (BIST), the CDR for the PHY is shown to recover data bursts in less than 50 ns even in the presence of high jitter specified in draft standard (0.76 UI @ BER= 1E-3). The device's serial input port employs a multivoltage-compatible CML interface, allowing it to be directly coupled to the PMD device supporting any CML interface ranging between 0.5 and 3.3 V. The company claims this eliminates the need for an AC coupling capacitor whose long settling time would have added overhead to the system. Parallel ports employ 17-bit transmit and receive interface designed around OIF's SFI-4.1 specifications and operate at 644 Mbps.
In general, when data input jitter is high, faster clock recovery is associated with higher jitter in the recovered clock, thus degrading the bit-error rate and making it difficult to implement forward-error correction. The conflict is reportedly resolved by careful control of burst mode period and CDR design optimization. Registration with a new ONU can be achieved within 400 ns without complex controls from MAC layer. "These features make the PHY 'user friendly' and facilitate easier system integration," adds Pathak.
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