Computing and managing power consumption for high-speed products
by Chintan Patel
Power management is one of the important considerations in high-speed and high-power applications. It is extremely crucial to calculate worst-case power consumption because the power specifications set the requirements for board layout to efficiently dissipate heat. There are two basic circuit technologies commonly used today, and they have very definitive characteristics. It is very easy to underestimate power dissipation (or consumption) without fully understanding their characteristics. This may lead to reliability concerns or overestimating power dissipation and costly redesigns.
While selecting a part or while calculating the power consumption, system engineers often rely on the maximum current or power stated in the data sheet. Although it seems logical to use this value, they forget to factor in frequency and loading at the inputs and outputs. Manufacturers do not include I/O loading power in their data sheet specs because not all the inputs and outputs are used in every application. Furthermore, the actual loading may change with power supply voltage. It is critical to use the current consumed by the load because loading power can be as much as the power consumed by the core circuit. Typical values are used in the calculations that follow.
The two basic circuit technologies are single-ended totem pole switching (such as TTL and CMOS) and differential current mode switching (such as PECL, CML, and LVDS). In single-ended totem pole switching, power dissipation is frequency and capacitive load dependent. On the other hand, power dissipation of differential current mode switching is typically not dependent on frequency or load capacitance.
where N is the number of used inputs; PI is power consumed by passive input termination; ICC is static supply current; VCC is the power supply voltage; CEQ is the equivalent node capacitance of the core circuit; f is the operating frequency; M is the number of used outputs; PO is power due to passive output termination; and CL is the load capacitance.
While calculating the input loading power, terminations external to the part should not be taken into consideration. On the other hand, terminations internal to the part must be used to calculate the power consumption of the chip.
Figure 1a shows interfacing between an LVPECL receiver and an LVPECL driver. Since the line is terminated externally, there is no power consumed by the chip at the input. Figure 1b shows an LVPECL driver interfaced to Micrel's AnyIn (internal termination) structure. The power consumed by Rb must be added to the total power consumed by the part because resistors Rb are internal to the device.
The power consumed by the core circuit (PC) can be simply calculated from the power supply voltage and the current stated in the DC electrical table in the datasheet. Since the power consumed by the differential current mode switching doesn't depend on frequency, core circuit power is the product of VCC and ICC:
Power consumption due to output loading changes from one differential logic to another. On one hand, PECL termination adds to the total power consumed by the chip; on the other hand, CML output structure shares current with the external termination, in turn reducing the power consumption of the chip. Unlike totem pole switching, differential current mode outputs are balanced; thus the loading power is not dependent on frequency. Below are output structures and power consumption methods for PECL, CML, and LVDS signals.
PECL outputs: PECL output structure is an open emitter transistor. To calculate the power across the transistors, first measure the current across the loads. Use this current to find the power consumed by the transistor pair (see Fig. 2).
Total power consumed PT = Input power (PI) + Core power (PC) + Output power (PO).
CML outputs: CML output is typically terminated 50 Ω-to-VCC. While calculating the output power due to loading, use the voltage drop from VCC to Q and /Q. Since the external resistors split the output buffer that is part of the core power, this external termination power needs to be subtracted (see Fig. 3).
Total power consumed (PT) = Input power (PI) + Core power (PC) â�� Output power (PO).
LVDS outputs: The output of an LVDS structure is the emitter connected to a current source. LVDS is terminated 100 Â¿ differentially across the output pair (see Fig. 4). Since the current in the output structure is constant and power dissipated by the termination is off-chip, the total power consumed by the part is the chip power minus the termination power.
As an example, Micrel's SY89112U is a 1:12 LVPECL fanout buffer with a 2:1 multiplexer at the input. The power consumed by this part is the sum of input power, chip power, and output power. The total power consumption will be affected by the number of outputs used in an application. We will assume that a given application uses both inputs and all 12 outputs. In this case, Vspan>CC = 3.3 V. Typical ICC stated in the data sheet is 95 mA.
Total power = Total input power + Core power + Total output power = 52 mW + 314 mW + 360 mW = 726 mW (11)
Notice that the power required to drive the input and the output stages is nearly as much as that required to drive the core circuit. This highlights the importance of including the termination power in your calculations.
Unlike power calculations for differential product, totem pole output power calculations are dependent on frequency and capacitive loading. Power consumption for single-ended circuits is broken down into static and dynamic powers.
The power consumed by the part when connected to the supply voltage is the static power. All the states are either high or low, not switching. Thus, static power doesn't depend on capacitance or operating frequency. Static power consumption is very similar to the differential logic products discussed earlier.
On the other hand, dynamic power is the power consumed by the part when a signal is present at the input and/or output. This power is dependent on frequency and capacitance.
(CEQ Ã� VCC2 Ã� f + (M Ã� PO) +
(M Ã� CL Ã� VCC2 Ã� f) (12)
Typically, the output stage is a CMOS inverter. Ideally, at any given time, QC or QD is off. There is no direct path from VCC to GND inside the output structure. Thus, PI and PO is 0 W. In reality, when the output switches states, QC and QD can be on at the same time for a brief moment. This forces current from VCC to GND through both transistors, in turn increasing (transient) power. The transient power can be significant. The product manufacturer can provide this information.
The termination resistors RU and RDconsume power from the voltage supply, not the chip. Thus, the static power of the core circuit is a function of power supply and current.
The single-ended output structure is a totem pole circuit that drives the output load high and low by turning on QC and QD respectively. The dynamic current at the output loading is required to charge and discharge the capacitor and depends on the frequency. Along with power supply and frequency, the dynamic power of the input structure and the core circuit are dependent on input and core capacitance respectively.
For example, a typical single-ended OR gate will consume 45-mA static current at 3.3 V. Assume this part is running at 125 MHz. All the values required to calculate the power consumption are provided in the table below. These values are usually provided in the data sheet.
Using the formulas above and the values from the table,
CEQ Ã� VCC2 Ã� f = 27 mW
M Ã� CLÃ� VCC2 Ã� f = 20 mW (13)
PTOTAL = 196 mW
Power management is a crucial step in every application. While designing a system or calculating power consumption, consider input and output structure power dissipation. While power consumed by differential current mode parts doesn't change with frequency, power consumption of single-ended parts is dependent on frequency and capacitance. The total power consumed varies with logic too.
Chintan Patel is a product marketing engineer at Micrel Inc. (www.micrel.com).