March 23, 2005 Austin, TX -- Silicon Laboratories, a designer of high-performance, analog-intensive, mixed-signal integrated circuits (ICs) for a range of applications, has introduced its Si5318 SONET/SDH precision clock multiplier IC, which according to the company delivers jitter generation in SONET/SDH line cards as low as 0.7 ps RMS, significantly lower than OC-48/STM-16 jitter specifications, while requiring no external components, and less than one-fifth the board space of discrete platforms.
According to the company, unlike similar products based on hybrid combinations of analog circuitry, crystals, or SAW-based oscillator elements, its precision clock ICs are based on its patented DSPLL technology, which uses digital signal processing techniques to create a fully integrated phase-locked loop (PLL).
The company says the wide tuning range of its DSPLL enables one design to support a broad range of frequencies that would traditionally require multiple crystal or SAW-based PLLs. According to the company, this frequency agility allows one Si5318 design to handle both SONET/SDH and forward error correction (FEC) rates, minimizing bill-of-material complexity and reducing R&D expense.
"The Si5318 is the smallest, most highly integrated jitter attenuating PLL IC designed for the OC-48/STM-16 market," contends Brad Fluke, vice president and general manager of Silicon Laboratories.
The company says its DSPLL technology relies on a low- phase noise, high-frequency, on-chip, digitally-controlled oscillator (DCO) to produce a frequency-agile, low- jitter output clock. The low- phase noise characteristic of the silicon-based DCO enables narrowband loop operation for applications requiring jitter attenuation. The IC provides user-selectable loop filter bandwidths ranging from 800 Hz to 12800 kHz, allowing users to easily match the level of jitter attenuation to the amount of clock cleaning required by the application, a feature not available with discrete PLL solutions, according to the company.
According to the company, by integrating all PLL components into a single device, its DSPLL provides greater immunity to system noise sources, while simplifying layout. The company says that competitive platforms built with discrete PLL components have multiple noise entry points, which require special layout precautions to protect sensitive analog nodes from board level noise that can increase clock jitter. The company's IC generates a single output clock in the 19 or 155 MHz range from a reference input ranging in frequency from 19 to 155 MHz.
The Si5318 is packaged in a 9 x 9 mm CBGA, and is priced at $32.00 in quantities of 1000. Samples are now available, with volume production projected for July 2005. An evaluation board, the Si5318-EVB, is also available for $350.