MSPP-on-a-chip enables SDH/SONET access edge deployment

May 17, 2005
May 17, 2005 Sunnyvale, CA -- Crimson Microsystems has launched its Ruby CM4800 "MSPP-on-a-chip", which the company says is designed to enable fully SDH/SONET-compliant multiservice provisioning platforms (MSPPs) for deployment at the network's access edge.

May 17, 2005 Sunnyvale, CA -- Crimson Microsystems has launched its Ruby CM4800 "MSPP-on-a-chip", which the company says is designed to enable fully SDH/SONET-compliant multiservice provisioning platforms (MSPPs) for deployment at the network's access edge.

The company says the CM4800 is a single-chip platform especially designed to enable the development of full-featured access edge MSPPs. According to the company, replacing up to eight discrete components, the chip's integrated design incorporates all necessary framing, pointer processing, high and low order crossconnect, and path termination functions for complete, STM-1/4/16 (and equivalent OC-3/12/48) SDH/SONET systems. With integrated support for both SDH/SONET line- and ring-based protection schemes and a 22.5 Gigabit crossconnect, MSPPs based on the chip can be deployed either directly on a SDH/SONET access ring, or as customer-located equipment on SDH/SONET access links, according to the company.

The chip integrates a multirate SDH/SONET VT/TU pointer processor with a multirate framer capable of supporting full line and path termination for multiple STM-1/4/16 (OC-3/12/48) streams. A 22.5-Gbit non-blocking, fully-channelized High Order (AU/STS) and Low Order (TU/VT) crossconnect enables on-chip grooming and line- or path-based protection switching to and from redundant backplane interfaces, as well as add/drop to and from a 2.5-Gbit, 77.76-MHz telecom bus interface. Supported protection switching schemes include MSP/APS, SNCP/UPSR, and MS-SPring/BLSR.

According to the company, the chip provides all necessary SDH/SONET processing for up to four STM-16/OC-48s, sixteen STM-4/OC-12s, or sixteen STM-1/OC-3s. The chip can be configured to support a mix of STM-1/OC-3, STM-4/OC-12 and STM-16/OC-48 lines/rings; the chip's pointer processor, path termination, and crossconnect simultaneously support any combination of both high and low order paths.

All functions can be controlled and monitored using an external processor; however, the company notes that an on-chip, 32-bit control plane processor can also be employed for provisioning, performance monitoring, and protection switching, significantly reducing the burden on external processors.

The chip is implemented using a 0.13-µm, low-power CMOS process, and comes in a thermally-enhanced FCBGA package, according to the company.

Currently sampling, the chip is priced at $500 in volume.

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