Vitesse teams with MOSIS on InP IC foundry
15 January 2003 -- Vitesse Semiconductor is providing indium phosphide hetero-junction bipolar transistor foundry services through MOSIS, a provider of prototyping and small-volume production services for IC and optical IC development.
15 January 2003 -- Vitesse Semiconductor Corp says it is the first company to provide indium phosphide (InP) hetero-junction bipolar transistor (HBT) foundry services through MOSIS, a provider of low-cost prototyping and small-volume production services for IC (and optical IC) development.
By working directly with MOSIS, customers will have access to Vitesse's proprietary InP VIP-1 technology. The VIP-1 process includes high-performance single HBT (SHBT) devices with other active and passive devices and multiple levels of metal interconnect. This process has been qualified for production usage and has an expected turnaround time for prototype circuits of 13 weeks, which is more than twice as fast as competitive technologies such as silicon-germanium (SiGe), it is claimed. Quarterly fabrication runs are planned initially.
The VIP-1 process offers circuit designers the benefits of both high-speed and high-voltage operation suitable for digital, analogue and RF circuits at 10GHz or higher. The process uses 4" diameter semi-insulating substrates and is designed for high performance and high yield.
The key active device is an SHBT, characterized by a threshold frequency (fT) of 150GHz, a maximum frequency (Fmax) of 150GHz (at a collector current IC=1mA/µm), and breakdown voltage BVCEO in excess of 4.5V. The process also includes resistors and capacitors, and three layers of metal interconnect. Device models and design rules are supported in the Cadence design environment and the robust process supports junction temperatures of 125 degrees C.
"The access to volume manufacturing capability at a low cost and fast turnaround time is key to the wide spread adoption and usage of InP technology," said Ray Milano, vice president of Physical Media Devices at Vitesse.
MOSIS will provide access to device models and design rules as well as reticle composition and overall schedule coordination. The circuit elements provided will include continuously scaleable parameterised cell transistors, resistors and capacitors, and ESD structures. Models are also available in ADS for microwave circuit design activity.