- Second generation NPU "sets a new standard" for performance and integration for midrange enterprise and low end metro Ethernet designs.
21 October 2003 Stockholm Lightwave Europe -- Xelerated today announced its second generation network processor - the Xelerator X11. Based on Xelerated's data flow architecture, the company says, "the X11 will bring high function, low cost network processors to midrange enterprise and low end metro Ethernet designs."
The X11 is a 20 Gbit/s network processor that leverages the patent pending PISC data flow architecture introduced by Xelerated's first generation network processor, the X10q. This is claimed to be the only multiprocessor architecture that offers the efficiency of a synchronous pipeline with the ease of programming of a uni-processor.
In the X11 data flow pipeline each packet passes through 360 PISC processors, raising the performance standard established by the X10q by 80%. Integrated 10 Gbit/s MACs with programmable XAUI interfaces allow direct connection to enterprise switch fabrics and Ethernet transceivers.
Integrated algorithmic search co-processors allow direct connection of high performance DRAM without consuming additional processing resources. Table search bandwidth has been increased to 110 Gbit/s to support high functionality applications, including advanced IPv6, while using inexpensive DRAM. Xelerated will disclose the architectural details of the X11 at the Network Processor Conference in San Jose, CA on 23 October 2003.
Gary Lidington, VP Marketing at Xelerated, said, "Our second generation data flow processor is more efficient than our first, allowing us to drive deeper into the enterprise market, while maintaining full software compatibility.
"The availability of high performance, low cost, programmable architectures such as the X11, will facilitate graceful integration of IPv6 into the enterprise, catering for swift response to changes as networks gradually integrate IPv6 into the current IPv4-based networks," said Latif Ladid, President, IPv6 Forum and Chair European Union IPv6 Task Force.
"Xelerated has established a clear lead in cost and power with the X10q-e. The X11 should extend this lead by integrating 10 Gbit/s MACs with a XAUI interface," says Bob Wheeler, senior analyst at The Linley Group.
And John G. Metz, president of the analyst firm Metz International, added, "The X11 demonstrates the scalability of Xelerated's data flow architecture. Employing the same proven process technology as the X10q, the X11 provides the equivalent of 360 processors, while maintaining software compatibility and a synchronous uni-processor programming model.
The Xelerator X11 is implemented in 0.13µm technology, and will sample in the third quarter of 2004.