Zarlink releases off-the-shelf digital timing chip
29 April 2003 Ottawa, Ontario Lightwave-- Zarlink Semiconductor today launched a high-speed digital timing chip that allows access and metro equipment designers to meet SONET/SDH network synchronization requirements.
29 April 2003 Ottawa, Ontario Lightwave-- Zarlink Semiconductor today launched a high-speed digital timing chip that allows access and metro equipment designers to meet SONET/SDH network synchronization requirements.
To avoid network errors, SONET/SDH standards stipulate that all system elements, including a diverse range of access and metro equipment, comply with stringent specifications for network timing and synchronization. As a result, SONET/SDH equipment must be equipped with timing circuitry capable of generating carefully controlled output clocks.
Zarlink's ZL30407TM digital PLL (phase locked loop) chip delivers an extensive set of output clocks and reliability features that simplify, shrink, and lower the cost of standards-compliant timing circuits for access and metro equipment. The device complies fully with Telcordia's GR-1244 and GR-253 standards for SONET minimum and Stratum 3 clocks, and the ITU's (International Telecommunication Union-Telecommunications) G.813 Option 1 and 2 for SDH clocks. In holdover mode, the ZL30407 meets the exacting demands of Stratum 3E and G.812.
Zarlink's new digital PLL features a 155.52-MHz output clock with very low jitter. Jitter, a short-term variation in clock timing, can cause data errors in optical networks. The worst-case jitter of the ZL30407 clock is only 325 picoseconds. (A picosecond is one trillionth of a second.) This high stability level allows the clock to link directly to OC-3/STM-1 interface chips without first being "cleaned" of jitter by external analog PLLs.
Several global equipment vendors are evaluating Zarlink's ZL30407 device for use on timing cards in DSLAMs (digital subscriber line access multiplexers), wireless infrastructure, digital loop carriers, and gateways. The device is also suitable for PDH (plesiochronous digital hierarchy) systems, and networking equipment with ST-BUS (serial telecom bus), GCI (general control interface), or H.110 backplanes.
Zarlink's ZL30407 digital PLL, by generating 10 different output clocks, supports a range of different framers, switches, mappers, and line interface chips. The high-speed 155.52-MHz LVDS (low-voltage differential signal) clock complements outputs operating at 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz, 16.348 MHz, 19.44 MHz, 34.368 MHz, and 44.736 MHz. In addition, the chip produces three 8-KHz (kilohertz) ST-BUS framing pulses.
The inputs on the ZL30407 chip are flexible. The PLL accepts frequency references from two independent sources, and synchronizes to any combination of 8 KHz, 1.544 MHz, 2.048 MHz, or 19.44 MHz.
The ZL30407 PLL has high-performance reliability features that enhance system integrity and ensure compliance with SONET/SDH standards. The two input reference signals are continuously monitored. If the primary reference drifts by more than 12 ppm (parts per million) from its preset frequency, the device immediately raises an alarm. This gives the system processor the forewarning needed to switch the ZL30407 PLL to its secondary reference before there is any perceptible impact
on its output clocks.
If both input references become corrupted, the chip seamlessly transfers into holdover mode. In holdover, the device generates a reference clock that is accurate to within 10-12, meeting the requirements of Stratum 3E. This clock remains stable for 30 times longer than Stratum 3 holdover clocks. Technicians thus have time to service equipment without undue interruption to subscriber services.
The ZL30407 PLL is now in production. The device is offered in an 80-pin LQFP (low quad flat pack) package measuring 14x14 mm. In quantities of 1,000, the chip is priced at U.S. $67.00.
