Programmable 40Gbit/s technology heads for mainstream Ethernet
29 April 2003 Stockholm, Sweden Lightwave Europe--Xelerated has launched the X10q-e Network Processor, which enables system vendors to build flexible, wire-speed solutions for the enterprise backbone and metro Ethernet markets.
- The X10q-e Network Processor sets new cost/performance standard at USD245 per 10G port.
29 April 2003 Stockholm, Sweden--Xelerated has launched the X10q-e Network Processor, which enables system vendors to build flexible, wire-speed solutions for the enterprise backbone and metro Ethernet markets.
The X10q reference design system running at 4x10Gbit/s will be demonstrated at NetWorld+Interop 2003 in Las Vegas between 29 April-1 May 2003 (booth 5938).
Low cost solutions for gigabit connectivity to the edge of the enterprise network are now available which is driving the need for cost effective, multi-port GbE and 10GbE line-card solutions for the enterprise backbone and metropolitan area networks.
Merchant silicon has played a leading role in driving down the cost of edge connectivity, but enterprise backbone and metropolitan area networks require a combination of wire speed performance and flexibility not offered by standard, off-the-shelf ASICs.
Xelerated's new data flow architecture (patent pending) allows the X10q-e to meet these requirements while maintaining the cost and power requirements of the enterprise.
"With the recent set of new product announcements it is clear that the multi-gigabit Ethernet wave is starting," says Michael Howard, principal analyst at Infonetics Research Inc. "The availability of innovative technology like the X10q-e will fuel that wave, enabling more cost-effective solutions for multi-gigabit enterprise backbone and metro Ethernet systems."
Hitherto programmable architectures have been burdened either by low performance, or high power dissipation, making them unsuitable for enterprise backbone equipment, leaving expensive custom ASICs as the only development choice.
"The speed with which Xelerated has moved from SDH/SONET to the Ethernet market is a testament to the flexibility of its architecture," says Linley Gwennap, principal analyst at the Linley Group. "And at less than 6.5W per 40Gbit/s they have set a new mark for network-processor efficiency."
"The lower packet rates of Ethernet relative to SDH/SONET have allowed us to scale back processing power and improve bandwidth efficiency relative to our SDH/SONET offerings - while still maintaining 40Gbit/s wire speed performance," says Gary Lidington, VP of marketing at Xelerated.
"The benefit we bring to our customers is that we have helped to level the playing field. Now they can build cost competitive, yet differentiated products for the enterprise - without spending tens of millions of dollars to develop all their own ASICs."
Xelerated's X10q range now includes two new offerings: the X10q-e and the X10q-m, each priced based on packet processing rate. The original 4x10Gbit/s SONET offering has been re-named the X10q-w. The original 2x10 and 1x10Gbit/s SDH/SONET offerings will be phased out over time.
As a part of these new offerings, the X10 will also support a new advanced search capability solution that leverages standard DRAM technology. This will reduce the cost of supporting large tables without stealing valuable processing cycles from the processor cores.
First silicon for the X10 was received in early January and customer demonstrations have been taking place since early February. "The response from our customer base has been very positive, and we are now working in a number of customer projects," says Johan BÃ¶rje, CEO of Xelerated.
Enabled by the availability of 0.13 micron process technology, the X10 architecture is the first known commercial implementation of a data flow processor. This architecture is optimised for the efficient movement of data, eliminating the need for complex inter-processor interconnects as well as redundant data and instruction storage.
This allows 200 data flow processors and ten I/O processors to fit on a single, low-cost chip providing unparalleled cost/performance. The 200 data flow processors are organized in a synchronous pipeline with each processor executing a single instruction. This makes them appear to the programmer as a single 80 BOPs processor with a fully deterministic execution time. The benefit over conventional multi-RISC based architectures is a much simpler programming model and guaranteed wire speed performance.
"We are very impressed with the X10q-e," says John G. Metz of Metz International in Harvard, MA. "Xelerated has taken race bred technology and made it practical enough for use on the street - no one we know can match their level of programmability, performance, power and price."
More information at xelerated.com