System-on-a-chip transport implementations can place total control of the SONET/SDH overhead and full crossconnect on a chip with no interconnect limitations.
As major carriers start to see service demands rise again, many are planning to deploy next-generation SONET/SDH equipment to lower capital and operational expenditures. Most carriers now operate with fewer network designers and managers; therefore, it is imperative that these new elements interoperate seamlessly with existing equipment. Also, as capital budgets remain significantly below their peak, network operators are demanding lower-cost equipment from their vendors. The trend toward data in the network will also increase as carriers deploy Ethernet and IP. Equipment vendors will thus need to look to advances in silicon technology to enable the features that carriers demand while meeting the new lower price points.
Fortunately, silicon VLSI technology has advanced significantly over the last few years, especially in the area of system-on-a-chip (SoC) development. In the commercial electronics market, SoC technology has been very successful. (You probably have a DVD player based on an SoC in your computer.) Similar advances now enable an entire add/drop multiplexer (ADM) to be built on a single piece of silicon. This high level of integration will generate dramatic reductions in cost and power while providing scalability, flexibility, density, and simplicity to build the next generation of data-aware SONET/SDH systems. The OC-192 transmission system that occupied an entire 7-ft bay of equipment in 1997 can now be built on a single card using an OC-192 ADM SoC implementation (see Figure 1).
In general, the optical transport industry has been slow to take advantage of SoC technology, due primarily a division within the industry between merchant silicon providers and systems developers. Traditional merchant silicon providers typically design "building block" ASICs that can be combined by systems vendors into a multitude of elements, line cards, and subsystems. These silicon providers generally lack the overall system knowledge required to define a complete SoC that would meet carriers' requirements. The system providers, on the other hand, generally lack expertise in designing state-of-the-art submicron VLSI silicon. There have been notable success stories of system vendors building a system in concert with an ASIC team—think Juniper Networks or Cerent (bought by Cisco Systems)—demonstrating the power of having systems expertise and silicon expertise under the same roof. However, none of the systems emerging from those companies was as highly integrated as SoC technology promises to enable, and none of those systems resulted in a silicon product that could be used by multiple vendors. Fortunately, companies with cross-functional teams are now emerging to provide commercial SoC solutions to the network-element vendor community.
The successful construction of a SONET/SDH transport SoC requires a cross-functional team with carrier-grade transport system design experience combined with an experienced submicron SoC design team. System-level expertise—from hardware design to software design to system engineering based on carrier interaction—can drive silicon design in ways that would not be considered by a traditional merchant silicon vendor.
As an example, consider the following feedback loop used when developing the crossconnect functions of a SONET/SDH SoC. Systems engineering demands the crossconnect be fully flexible (any port to any port, virtual concatenation support, etc.). Based on that requirement, hardware design determines the size and read/write speed required of the crossconnect. Based on the hardware and systems requirements, silicon designers develop a basic crossconnect design. Software expertise is called in to determine if the scheme can be operated efficiently and at speed. Any tradeoffs can be fed back to systems engineering to verify there will be no impact on the performance expected by carriers and systems vendors.
The combination of systems expertise and silicon expertise can also result in features that would not be considered by either team alone. For example, network studies performed with large carriers have shown the benefit of having programmable-rate low-speed ports (e.g., OC-3, OC-12, Gigabit Ethernet, or OC-48). Systems designers familiar only with conventional building-block silicon might not consider such flexibility in their hardware design. ASIC designers would look at a port that is capable of running at OC-48 speeds and consider running it at OC-3 rates to be a waste of resources. In fact, products available from traditional silicon designers usually allow OC-48 ports to be run either at full speed or as 16 separate OC-3s to better use the port resources.
However, system designers with a firm grasp on network deployments understand that usually there is a mix of rates required at any one location. Network-element architectures that require deploying a 16-port OC-3 card when only a single OC-3 is needed are unnecessarily expensive to the network designer. While deploying an OC-3 on a port that could run at OC-48 rates may be an underutilization of resources, it can still represent measurable savings in capital expense for the end user. By truly understanding not only the capabilities of silicon, but also the requirements of network architects, SoC features can be designed that result in significant savings for network operators.
Transport SoC designs must be able to integrate with legacy SONET/SDH networks. Although systems expertise is usually helpful in interpreting the standards, the SONET/SDH standards are relatively well known throughout both industries. However, the flexibility of controlling the entire system on a single piece of silicon allows for extensions to the standards that would not otherwise be possible. Designing these extensions based on an understanding of network implementations can result in evolutionary improvements in transport networks that would not otherwise be possible.
SoC transport implementations can place total control of the SONET/SDH overhead as well as the full crossconnect on a chip with no interconnect limitations. The result is the ability to use SONET and SDH transport in ways that have not been possible in the past. One example is SONET mesh networks, in which the rigorous relationship between protection domains and physical links can be broken to create a SONET-based mesh network that is guaranteed to restore in 50 msec or less.* Fully flexible access to overhead and crossconnect functions can allow multiple K1/K2 protocols to run on the same physical line, enabling multiple bidirectional line-switched rings to share a common span. Changes in standards can be quickly implemented through software changes alone, and vendors that choose to use undefined overhead bytes for proprietary purposes (e.g., extended DCC-like channels) can implement changes or turn off features for interoperability via software coding.
One often-overlooked benefit of SoC implementation is power savings. Power is a significant concern for major carriers as denser next-generation equipment begins to stretch their already overburdened power budgets. One RBOC claims to spend $500 million a year on power alone, and many central offices are already at their power-handling limit.
A majority of the power (about 70%) required to run ASICs is consumed by the interfaces to the surrounding components. By combining multiple components onto a single chip, the number of interfaces is greatly reduced, with a corresponding reduction in power consumption. For example, consider a SONET ADM implementation. Using standard silicon, a network designer would be required to interconnect two line-rate framers, four to eight tributary rate framers, and a crossconnect. Between these chips are up to 10 interchip interfaces, some of which are running at power-hungry high speeds. Combining all this functionality onto an SoC eliminates all 10 interfaces completely, with the result that such chips have been shown to use less than 20% of the power of the multichip solution (see Figure 2).
Along with a reduction in power, combining multiple functions onto a single chip results in a reduction in complexity and cost. Much of the design work required in building next-generation SONET/SDH hardware goes into defining and laying out the interconnections between the building-block chips. With an SoC implementation, many of those design hurdles disappear, resulting in the potential for much faster time-to-market and significantly lower development risk.
SoC implementations are poised to revolutionize the SONET/SDH transport market in much the same way they have revolutionized other applications. Building an entire transport system on a single piece of silicon using a cross-functional team with systems and silicon expertise can result in significant cost, power, and complexity savings while enabling an entirely new set of features and functionality. These innovations, timed just as the telecommunications market is poised to recover, will offer a powerful economic incentive to network operators to reinvest in their networks as part of the evolution of SONET/SDH networks into the next generation of lower-cost, higher-functionality, converged data/voice transport networks.
Scott T. Wilkinson is marketing vice president at Parama Networks Inc., 672 Gunby Rd., Marietta, GA 30067. He can be reached at email@example.com.
* "SONET Mesh Network Architecture," Scott T. Wilkinson, S. Raguram, P. Limaye (Parama Networks), and E. Bert Basch, Vishnu Shukla, Peter Kubat (Verizon Laboratories), presented at NFOEC 2003.