Cost-effective OC-768 systems
Infineon offers a closer look at what it claims to be the industry's first 40Gbit/s framer.
By Srinvas Nimmagadca and Rocco Falcomato
Infineon Technologies North America Corp
Transport system developers face many challenges, including increasing the bit rate per channel while considering growing cost pressure and the need for standards compliance. Survival in the telecoms industry also calls for high speed, small footprints and quick time-to-market.
Infineon says that its Titan 19244 framer is the industry's first highly integrated single-chip, single-port OC-768 or quad-port OC-192 SONET/SDH TDM framer and pointer processor, enabling scale-up of next-generation systems to 40Gbit/s and beyond.
- STS-1 level pointer processing
Allowing for each STS-1's pointer state to be stored away in synchronous memories allows for fewer copies of the pointer processor logic and reduces chip area and power. The Titan's sequencer design makes it the first device to support pointer processing for every STS-1 in an STS-768 frame. Also, a novel FIFO memory architecture reduces die area and power by implementing 768 plesiochronous synchronisers to absorb the clock frequency difference between the line and system clocks.
- Flexible concatenation
The Titan supports pointer processing and path overhead processing for non-standard concatenated channels. Typical framers support only STS-3Nc, (concatenations of multiples of three). Titan can support any concatenation, from STS-2c to STS-191c, allowing allocation of exactly the bandwidth required (important at higher data rates like 40Gbit/s). To support this, a scheme was devised to handle the provisioning and processing of such channels, requiring timing precision and sophisticated layout techniques to implement high-speed, large multi-port register files.
- Flexible service provisioning
Carrier-class, next-gen multi-service optical transport platforms need flexible service provisioning to guarantee faultless provisioning. The Titan allows for provisioning of any type of channel, service, concatenation level, and performance monitoring for each individual channel. For example, both SONET and SDH channels can be intermingled, any concatenation up to 192c can be provisioned and mixed with any other concatenation, and any number of fixed stuff bytes can be programmed for each channel. Also, Titan implements a scheme that ensures that a service can be brought down and new services provisioned without fault inducement on existing services.
Framing at the speed of light
Facing the challenges of greater functional integration with lower power consumption, the Titan 19244 implements the salient features while providing section, line, and path overhead processing for single STS-768/STM-256 or quad STS-192/STM-64. Power dissipation of about 10W provides a greater than 50% saving compared to discrete chip-set solutions.
For next-gen systems, Titan complies with the SFI-4 standard on both line and system side, supporting four full-duplex 10Gbit/s (16-bit bus at 622Mbit/s) channels, and with SONET/SDH standards ITU G.707, Bellcore GR-253, GR-1377, and ANSI T1.105.
In the field
Titan can be applied to long-haul and metro DWDM, next-gen SONET ADM and DCS systems.
In Figure 1 it aggregates four STS-192 streams into an STS-768 stream. With SFI-4 interfaces on both sides, it receives four 10Gbit/s streams on the STS-192 side, while downstream it demultiplexes an incoming STS-768 stream into four STS-192 streams. By using its STS-1 level pointer processing downstream it can support independent clock domains on line and system sides, enabling the handing off of four STS-192s to four independent system-side clients.
Infineon Technologies' Titan 19244 IC supports a variety of interfaces: the line side and system side are SFI-4 compliant full-duplex 16-bit interfaces operating at a speed of 622Mbit/s; the microprocessor interface is 32-bit operating at 66MHz and supports the Motorola standard. All Transport Overhead (TOH) bytes and Data Communications Channels (DCC) can be dropped and added on the line and system side through proprietary interfaces operating at 77MHz.
The receive line and transmit system interface blocks implement the high-speed demux circuits as well as the SONET deframer and descrambler blocks. These include all standard SONET performance monitoring and alarm detection for LOS, LOF, SEF and AIS-L alarms as well as B1/B2 bit error rate algorithms. Also, frame alignment to the A1/A2 bytes is implemented, as well as processing for the B1, B2, K1/K2, M0/M1, D1-D12 and S1 bytes.
The receive system and transmit line interface blocks implement high-speed mux circuits as well as the SONET framer and scrambler blocks. These include insertion of all standard SONET section and line overhead bytes from internal registers or via an external inteface.
The receive pointer processor and path processor block performs processing of all 768 paths and follows all the SONET rules of pointer interpretation and generation. Each payload is extracted and passed from line to system side through plesiochronous FIFOs. Standard required alarm detection for LOP, UNEQ, PLM, REI and AISP are reported through the microprocessor interface. Also, processing for the J1, C2, G1 and B3 bytes is supported.
The Titan 19244 comes with a complete board design package including reference design, layout support and design rules, as well as software support including drivers and APIs.