Single-chip 12.5Gbit/s switching
The first single-chip 12.5Gbit/s asynchronous optical cross-point switch reduces power consumption and jitter for metro and long-haul network applications.
Valerie Leclerc, Application Support Philips Semiconductors
Philips Semiconductors of Eindhoven, The Netherlands, is sampling what it claims is the first single-chip 12.5Gbit/s asynchronous optical cross-point switch. The 20x20 TZA2060 has uni-cast, multi-cast and broadcast switching capabilities and will help bring protocols like 10 Gigabit Ethernet, SONET and SDH to metro and wide area networks (MANs and WANs).
Increased bandwidth is leading to more input and output ports - with faster data rates - for the switch fabric, needing high-speed and high-density cross-point switches. But, due to technology limitations, the density of a desired switch fabric often exceeds the capacity of a single chip.
"As Internet service providers, telecoms and network operators upgrade their networks to handle streaming media and broadband datacom services, the need for data-routing optical exchange equipment will proliferate," says Jos Lammerts, general manager networking infrastructure. "The lack of suitable network termination and switching equipment has so far prevented such organisations from taking full advantage of the potential bandwidth and scalability of available network technologies. The TZA2060 will be a key component in cost efficient and scalable applications such as ADMs and cross-connects in DWDM systems."
The new generation of optical cross-connects - one of the fastest-growing applications in optical networking - will replace older digital cross-connects by enabling switching at native line rates up to 12.5Gbit/s.
Single-chip 12.5Gbit/s switching is enabled by QUBiC4'G' high-speed and low-power silicon-germanium technology. "Throughout the entire development of QUBiC4'G', we worked closely with our optical networking business line in order to speed up the introduction of their new products," says Neil Morris, senior director of advanced technology, Philips' semiconductor division.
The design maintains highly symmetrical rise and fall times and cuts jitter to <2ps per switch. This allows cascade of up to three TZA2060 switches without the need to insert clock/data recovery and re-timing logic. In complex systems such as Clos switches, this cuts component count, PCB area, and equipment manufacturing costs.
Power consumption is crucial since, due to the three-stage Clos architecture, a large switch fabric can be built by combining between nine and over 600 switches.
The high-signal integrity 20x20 TZA2060 provides power consumption of <3W and a maximum of 0.2UI peak-to-peak jitter when all inputs and outputs are activated with the maximal differential swing.
For 1.28TGbit/s aggregated bandwidth, 48 16x16 OC-192 switches can form a 128x128 asynchronous switch fabric consuming <144W (0.11W per Gbit/s, Fig. 2), whereas 48 64x64 3.2Gbit/s OC-48 switches in a 512x512 fabric consume 432W even with the Philips part (9W with all inputs and outputs activated). A power-down option for each input and output also cuts consumption from 144W to 100W (or 432W to 300W).
The design also allows routing of smaller amplitude signals, giving lower parasitic coupling. All the 12.5Gbit/s serial data inputs and outputs are Current-Mode Logic compatible.
The low power consumption and jitter also suits other applications such as backplane switching, storage area networks, high-speed test equipment and video switching.
The QUBiC4'G' fabrication process is intended for high-speed optical networking for broadband datacoms and streaming media. It enables the integration on the same chip of ultra-high-speed SiGe transistors with the existing QUBiC4 BiCMOS process's standard dense (0.25µm) CMOS logic, shallow- and deep-trench isolation (to minimise cross-talk and interference) and passive components.
Examples of these would be very high-density 5fF/µm metal-metal tantalum pentoxide capacitors and high-Q-factor inductors. The passive components are enhanced with the addition of impedance-matched transmission lines in the top two thick metal layers to cope with the demands of gigabit/s speeds.
A mix of high- and low-breakdown-voltage SiGe transistors allows a choice of fT, fmax, and noise figure: low-voltage (BVCE>2.7V) transistors: fT=75GHz and fmax=100GHz ensure the gain and phase margins needed to design highly linear amplifiers and transmission gates with fast and symmetrical rise/fall times and low jitter, even through multi-stage Clos switches; higher-voltage (BVCE>3.8V) high-frequency transistors to implement circuits such as VCOs or interface with external 3V logic.
The QUBiC4'G' process is available for design now, with volume wafer processing expected in Q3/2002.