Zarlink module sets benchmarks for central timing cards in access and metro communications equipment
10 December 2003 Ottawa, Canada Lightwave-- Zarlink Semiconductor today launched the ZL30461 timing module, the smallest, most fully featured timing product for central timing cards in SONET/SDH systems that provide clocking frequencies up to 155.52 MHz.
Designing highly reliable timing devices for central timing cards that comply with stringent SONET/SDH standards for network timing and synchronization is a key challenge for communications equipment makers. The ZL30461 module minimizes design risks by combining digital and analog PLL (phase-locked loop) technology and a 20-MHz master oscillator into a small, standards-compliant timing device. The module offers 14 output clocks the industry's widest range of clocks for SONET/SDH timing cards without requiring external components or complex programming.
"In-house design and testing of timing and synchronization devices is often a costly, time-consuming process," said Darren Ladouceur, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "Our ZL30461 module is a full-function, off-the-shelf device that meets worldwide standards for central timing cards."
Equipment vendors are evaluating the ZL30461 module for SONET/SDH central timing cards used in DSLAMs (digital subscriber line access multiplexers), media gateways, add/drop multiplexers, Internet routers, and network access equipment. The module can also be used on line cards in network element equipment. Coupled with the ZL30462 timing module for Stratum 4 and STM-1 applications, Zarlink now offers modules for both line cards and central timing cards in SONET/SDH equipment.
The ZL30461 device is a System-in-Package module measuring 23x23 mm, or less than 1 square inch--the smallest footprint in its class--and approximately 75% smaller than competing products.
Zarlink's module complies with Telcordia's GR-253-CORE standard for SONET Stratum 3, GR-1244-CORE standard for Stratum 3, and the ITU-T's (International Telecommunication Union-Telecommunications) G.812 and G.813 Option 1 and 2 standards for SDH equipment clocks (SEC). The module exceeds OC-12/STM-4 jitter requirements at rates typically less than 7-psec RMS (root mean square).
To ensure the level of reliability necessary for central timing cards, the ZL30461 module offers "hitless" reference switching and holdover. The device monitors both input references, and if the primary input is interrupted the module enters holdover mode, generating its own reference clock based on data collated from past reference signals, while verifying the integrity of the secondary reference. If the secondary reference is also corrupted, the module can maintain holdover for over 24 hours, a common system requirement that allows service providers to maintain service while problems are resolved.
Delivering 14 output clocks, Zarlink's highly flexible ZL30461 module produces two ultra-low jitter clocks a 77.76-MHz LVPECL (low-voltage pseudo emitter-coupled logic) clock, and a 19.44 MHz CMOS (complementary metal oxide silicon) clock as well as jitter-attenuated clocks operating at 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz, 34.368/44.736 MHz, and 155.52 MHz. The module also produces three ST BUS compatible 8 KHz frame pulses.
The inputs of the timing module accept frequency references from two independent sources programmable for operation at 8 kHz, 1.544 MHz, 2.048 MHz, or 19.44 MHz.
Availability, packaging and price
Zarlink's ZL30461 timing module is in volume production. In quantities of 1000, the module is priced at US $164.00. The device is offered in a 240-pin BGA (ball grid array) package measuring 23x23 mm. A reference board is available for testing and evaluation.