Hybrid integration of components catches high-speed signals

Mark Itzler and Sabbir Rangwala

Tremendously rapid growth poses enormous challenges to the entire supply chain of products needed to assemble fiberoptic systems. Fiberoptic receiver components are critical elements in this supply chain, and several major themes play a role in their future evolution.

First, the steady migration to higher transmission bit rates is accompanied by a shift in the supplied component interface to the customer's module. This trend dictates the second theme, which is increased hybrid integration at the component level of traditionally discrete electronic elements. Third, more optical content will precede the photodetector, and this optical integration may eventually attain a scope comparable to the electronics integration following the detector. Finally, the rapid evolution of the systems marketplace and the challenges inherent in engineering high-speed receiver components require tremendous flexibility, rapid and robust product development, and very short time-to-volume intervals from component suppliers.

RECEIVER COMPONENT EVOLUTION
A fiberoptic receiver is required at every point in the network where an optical-to-electrical signal conversion is needed. This functionality, which becomes more difficult to achieve as higher bit rates are introduced, is realized using a fairly long chain of elements (see Fig. 1).

An optical fiber must be coupled to a photodiode to generate photocurrent. Using a transimpedance amplifier (TIA), the photocurrent is converted to an analog voltage that is further amplified by a post amplifier. Digital integrated circuits are then needed to generate a clock signal, recover the data, and demultiplex the data to lower-rate electrical bit streams. At high bit rates, the total functionality of a high performance receiver is often achieved using several lower level components by discretely assembling these into a fully functional module. One of these components typically contains the fiber-coupled photodiode packaged with the analog electronics (such as the TIA and perhaps a post-amplifier) and is referred to as the "analog front-end" of the receiver.

It is interesting to analyze how the optimal level to which integration of various receiver functions at the component level has varied with the bit rate (see Fig. 2). At low speeds (less than 2.5 Gbit/s), the optimal interface for the component was a photodiode chip coupled to a fiber. From the perspectives of technology, flexibility, and cost, it made sense for a module manufacturer to integrate all of the analog and digital functionalities.

At 10 Gbit/s, while analog front-end receivers provide an extremely popular product interface, the complexity of testing conditions and the dependence of the performance on specific module board-level layout requires very customized interactions with each customer. There are also clear opportunities for component vendors to add tremendous value by integrating digital and demultiplexing functionalities for their customers in some segments of the applications. Therefore, a full 3R (regeneration, reshaping, and retiming) receiver within a component footprint becomes desirable. The trend will continue with 40-Gbit/s receivers.

INTEGRATION APPROACHES
Providing an analog interface at the receiver component level presents tremendous mechanical and electrical interface challenges for the board manufacturer (see Fig. 3, top). Simulations show that interface misalignments on the order of a few tens of microns can severely degrade bandwidth performance. Necessary assembly capabilities are frequently beyond normal tolerances for board-level manufacturing, so it may become critical to integrate digital and demultiplexing functionality within the component, reducing the complexity for the board- and system-level customers (see Fig. 3, bottom).

Three critical issues need to be addressed to define where the value-added interface should lie. Technical complexity: Can increased hybrid integration minimize technical complexity and performance degradation at the board level? Assembly costs: Can higher level functional integration be achieved at the component level at a competitive cost? Design flexibility: Will design flexibility at the board level be unacceptably inhibited by increased integration?

To achieve complex functionality such as the recovery of a high bit-rate digital optical signal, lower level functions must be integrated. Chip-level devices provide these functions, and the interconnection of these chips can be achieved using one of three broad concepts. Discrete integration can be accomplished by first packaging each chip in a separate housing and then connecting these housings together, often with a board-level assembly. Hybrid integration provides for the assembly of numerous chip-level components into a single housing. Finally, monolithic integration allows for the combination of multiple functionalities in a single chip made from one material system.

Typically, discrete solutions are the simplest to execute and are often used for a rapid, first-generation solution. However, the discrete interfaces between functional blocks usually result in performance compromises, high cost, and large form factors. Additionally, the discrete approach does not easily scale to large volume.

Hybrid solutions provide much of the flexibility of discrete integration by allowing the use of chips optimized for different functions, often from different material systems. However, with an appropriate assembly platform, high performance can be obtained with efficient, low-cost processes that can be scaled to large volume through automated assembly. Desired functionalities can be achieved in a single housing of reduced size with more intimate, well-controlled interfaces.

Monolithic integration provides the most efficient means of combining functionalities because they are imbedded in a single material system. Manufacturing of these chip-level devices can be massively parallel, enabling vastly reduced cost, reduced size, and the potential for very high performance. The challenge to this approach is that it can take decades of technological maturity (as in the silicon electronics industry) and requires the availability of a single material system that can realize all desired functionalities without undue compromises in performance.

Currently, there are two broad areas in which the push to more hybrid integration is intense. To achieve lower-cost products for high-volume applications, automated hybrid assembly and testing is essential. Receivers at 2.5 Gbit/s provided the highest bit rates available just a few years ago, but this performance is now required for metro and access markets in which costs must reach commodity levels. Moreover, customers are demanding transmit and receive functionalities in one device, so next-generation high-speed transceivers are becoming hybrid integrated components. At the same time, realizing 40 Gbit/s functionality is so difficult with discrete solutions that the push to hybrid solutions may be dictated by performance factors alone (see Fig. 4).

Monolithic integration of optoelectronic components may provide enormous benefit but will be extremely challenging. Unlike purely electrical functionality, for which silicon has proven to be a versatile material platform, optoelectronic and optical functions are realized using a wide variety of technologies and material systems. Of these various materials, indium phosphide (InP) is one of the more attractive possibilities for monolithic optoelectronic chips. It is already the best choice for telecommunications detectors and emitters, it may be the best choice for high-speed electronics integrated circuits, and it is possible to achieve optical functionality using waveguides and other micromachined structures.

If there are too many compromises in trying to achieve multiple functionalities in one material system, the monolithic approach will have to wait for improvements in the basic technologies. However, to the extent that a material system like InP is appropriate, today's components are likely to become tomorrow's chips. Likewise, as discrete approaches to designing fully integrated receivers give way to chip-level hybrid solutions occurring inside a single chassis, today's modules will become tomorrow's components (see "InGaAs avalanche photodiodes offer benefits," p. 42).

High-performance optical functions are already prevalent in instances where the digital signal is not being received, such as in the case of optical-performance monitoring. Filters have been hybridly integrated with photodetector monitors to achieve wavelength selectivity for uses such as the rejection of pump wavelengths (980 and 1480 nm) or the measurement of single wavelength channels. Higher functionality monitors are used to demultiplex the entire signal band to track channel power, center wavelength, and optical signal-to-noise ratios so that network functions such as gain equalization and wavelength locking can be provided.

Meanwhile, opportunities for optical integration at the receiver level are numerous. Integration of a tunable filter would allow the receiver to select any channel within the tuning range. A tunable receiver would be useful at reconfigurable add/drop sites as well as in WDM systems in which a small number of tunable receivers could be used to back up the much larger number of receivers used for each wavelength channel.

The integration of optical preamplification is another opportunity to improve receiver performance, especially in 40 Gbit/s receivers for which avalanche photodiodes will be very difficult to design. Erbium-doped fiber amplifiers already precede receivers in some network locations, and the more compact integration of erbium-doped waveguides or semiconductor optical amplifiers is attractive. Finally, with an appropriate device technology, it may eventually become possible to integrate in a hybrid fashion other optical functions that now precede the receiver, such as dispersion compensation.

PRODUCT DELIVERY
The delivery of receiver components (and, in general, of all fiberoptics components) is strongly impacted by the dynamics of the customer system requirements, the new-product development process, the ability to scale up volumes, and the supply chain required to build components.

The systems marketplace is intensely competitive with a few large and vertically integrated players plus many well-funded, aggressive start-ups. The start-ups have injected a new urgency and time scale into installing new and more-efficient system architectures to serve the ever-hungry communications marketplace (itself driven by more nontraditional service providers of data and voice services).

Whereas in the past the large system houses controlled the dynamics and time scales for new system versions and innovations, newer players have raised the ante in terms of delivering newer versions and innovations in shorter time intervals. Consequently, to serve the needs of the new market dynamics, component suppliers have had to find innovative ways to deliver new generations of components in much shorter timeframes than before.

There are various challenges to shrinking the new product development cycle and time-to-volume (TTV) requirements. As opposed to previous development processes that were highly serial, risk averse, and conservative in nature, newer processes require parallel approaches with explicit risk management, strong partnerships with customers, and a focus on rapid customer sampling and feedback with resultant design adjustments.

As the design process zeros in on the final version, intense planning is required to achieve a rapid volume ramp-up. Materials, equipment, process instructions, design documentation, and tooling all need to be planned at each step of the process so that no bottlenecks arise to prevent the rapid ramping. One of the most disadvantageous positions to be in is one in which customers are sampled with initial product versions, they like what they see, they place large volume orders, and they are then told that they will have to wait a long time until the volume ramp is achieved.

Three important factors that need to be considered to drive down product development and TTV intervals are:

Concurrent engineering and risk-sharing with key suppliers. In contrast to the fast-paced systems marketplace, dominated by quick moving and aggressive start-ups, vendors who sell to component developers are typically large corporations with long delivery cycles for prototypes and volume supply. While it is true that smaller vendors are generally quick to supply prototypes, they suffer with respect to high-quality volume supply. This handicup makes it difficult for component companies to follow up a successful prototyping phase with a smooth and rapid volume ramp.

The key is to work very closely with vital suppliers from the start of the design cycle. In many cases, it is critical that the relationship be so close that component designers understand in detail the design rules of their suppliers and design into these rules. This greatly reduces the long period of specification negotiations that typically ensue. Also, risks may have to be taken by ordering large volumes of material even prior to the prototyping stage to enable a quick ramp-up.

Designing into developed, robust process platforms. To minimize the risk to delivery of new, high-performance products, it is critical that the products are designed into well-understood and robust process platforms. Parallel development of new product designs and new process platforms greatly increases the complexities and risks associated with delivery of the new product on schedule.

Basing designs on well-understood reliability rules and test data. The trick here is again related to using well-understood, well-characterized process platforms, efficient use of reliability models, and the ability to test various subassemblies of the proposed design quickly from a reliability perspective. This approach greatly minimizes the risk of reliability test failures, and the consequent delays in product launch.

Mark Itzler is vice president and chief technology officer and Sabbir Rangwala is vice president of new product development at JDS Uniphase's West Trenton facilities. They can be reached at 609-406-7482 or [email protected].

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Increasing avalanche photodiode (APD) gain increases a receiver's signal-to-noise ratio (SNR) as long as the avalanche noise remains less than the noise of the preamplifier. Optimal receiver sensivity is obtained when avalanche noise is comparable to preamplifier noise.

The response of the canonical pin diode is intrinsically quantum-limited: each photon absorbed creates only a single electron-hole pair to contribute to the photocurrent. This limitation can be circumvented to obtain more photocurrent per photon by designing an avalanche photodiode (APD) in which carrier acceleration in a high-field multiplication region is sufficient to create additional carriers by impact ionization. This so-called avalanche process leads to internal gain.

The randomness of the avalanche process makes an APD inherently noisy relative to a pin diode. However, increasing the APD gain will increase a receiver's signal-to-noise ratio (SNR) as long as the avalanche noise remains less than the noise of the preamplifier (that dominates other receiver noise sources at high bit rates). The optimal receiver sensitivity is obtained for the gain M* at which the avalanche noise is comparable to the preamplifier noise (see figure). Typical 10 Gbits/s APD-based receivers show sensitivity improvements by 5 to 6 dB relative to comparable pin-based devices, and at 2.5 Gbit/s, sensitivity improves by 7 to 8 dB.