Sierra Monolithics unveils 100G mux/demux chipset
MARCH 16, 2009 â�� Following last month's introduction of 40-Gbps devices, Sierra Monolithics has unveiled what it touts as the world's first 100-Gbps multiplexer with CMU and demultiplexer with CDR.
MARCH 16, 2009 â�� Following last month's introduction of its 40-Gbps Epsilon devices, Sierra Monolithics (search Lightwave for Sierra Monolithics) has unveiled what it touts as the world's first 100-Gbps multiplexer with clock multiplier unit (CMU) and demultiplexer with clock and data recovery (CDR).
The Theta-100G devices are targeted at 100-Gbps transponder modules and line cards.
The chipset includes the SMI10021 10:4 mux/CMU and SMI10031 4:10 CDR/demux devices. Each uses the same fourth-generation, 130-nm IBM 8HP bipolar complementary metal-oxide semiconductor (BiCMOS) silicon germanium (SiGe) process technology as the company's 40-Gbps chips to enable small size and low cost and power consumption. Bipolar SiGE results in higher gain, higher frequency, and lower noise floor as compared to CMOS, allowing transmission systems to meet stringent eye quality parameters.
The Theta-100G chipset operates at 4x25.0 Gbps to 28.3 Gbps (100-113 Gbps aggregate) and incorporates an integrated, dual-polarization quadrature phase-shift keying (DP-DQPSK) modulation precoder function.
The Theta-100G chipset incorporates a 10x10.3-Gbps (MLD/CAUI) or 11x11.2-Gbps SFI-S interface on the client side, as well as a de-skew function in compliance with OIF SFI.S, plus a line-side pre-skew function for the MLD/CAUI interface with a depth of 84UI. The DQPSK precoding function is implemented with dual I/Q-interleaved outputs (4x28 Gbps) for dual-polarized applications. The precoding function may also be configured to enable a single-pole 2x56-Gbps DQPSK modulation structure with a pair of external 2:1 multiplexers through use of the synchronous high-speed clocks that may be programmed to any desired clock-to-data skew.
Other features include on-chip industry-standard selectable phase detector on-chip dual-mode (PRWS) pattern generators and error checkers, and SPI control interfaces with clock rates to at least 150 MHz. Typical jitter swing is 3.7 psec p-p typical, and the differential output level is 0.6 to 1.2 V p-p. Power consumption is 4 W max with high-speed clock outputs disabled.
"After years of delay, network operators finally are moving on a wide scale to deploy 40-Gbps DWDM in their networks," said Sterling Perrin, senior analyst with Heavy Reading. "But even as 40G begins to take hold, carriers already are anticipating a migration to 100G. The market eagerly awaits new products from suppliers of 100G chips, components, and systems that will make 100G technically and economically viable."
The Theta-100G SMI10021 and SMI10031 devices will sample in second quarter 2009, and are scheduled to enter volume production in the fourth quarter of 2009. They are packaged in a ball grid array (BGA).
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