Sierra Monolithics intros fourth-generation 40G mux/demux
FEBRUARY 11, 2009 -- Thanks to IBM's 8HP silicon germanium (SiGe) bipolar complementary metal oxide semiconductor (BiCMOS) process technology, Sierra Monolithics says its SMI4027 can support a range of data rates from 39.8 Gbps to 44.6 Gbps while simultaneously incorporating an on-chip, user-enabled DPSK precoder function.
FEBRUARY 11, 2009 -- Sierra Monolithics (search for Sierra Monolithics), supplier of high-performance ICs and modules for high-speed analog and RF applications, has introduced its fourth-generation 40G multiplexer with clock multiplier unit (CMU) and demultiplexer with clock and data recovery (CDR).
According to the company, the highly integrated devices incorporate all required pre-coding circuitry for long-reach applications and superior signal integrity and use IBM's proven 8HP silicon germanium (SiGe) bipolar complementary metal oxide semiconductor (BiCMOS) process technology to achieve significant power reductions compared to previous SERDES product generations.
"The SMI4027 MUX/CMU and SMI4037 CDR/DEMUX represent an important milestone in the development of the 40G-and-beyond optical transmission market," reports Taqi Mohiuddin, director of marketing with Sierra Monolithics. "It offers the size, cost, and power profile for mainstream 40G system deployment and helps deliver the system performance and transmission economics that carriers need in order to take the next big step in accommodating today's explosive growth in network bandwidth consumption over the existing fiber infrastructure."
Sierra Monolithics says it has been developing integrated circuits for a variety of communications applications using IBM's SiGe process technologies since 1996. The latest 130-nm generation of IBM's SiGe process doubles the performance of previous generations and also improves power efficiency and integration. These process advances enable the SMI4027 to support a range of data rates from 39.8 Gbps to 44.6 Gbps while simultaneously incorporating an on-chip, user-enabled differential phase shift keying (DPSK) precoder function. DPSK precoding is a key requirement both for long-reach applications and to provide the necessary resiliency against signal impairments that are often encountered in older fiber.
"In our 10/40/100G market study released last October, Infonetics reported that, despite the economic downturn, 40G was ramping rapidly, and 100G should begin soon and take off by 2013," reports principal analyst and co-founder of Infonetics Michael Howard. "These technologies are critical for alleviating the tremendous strain due to data center growth and consolidation, and video applications on business, consumer broadband, and mobile networks. Components in the supply chain such as these new 40G mux and demux devices from Sierra Monolithics will play a key role in helping to ensure that growing traffic demands don't outstrip network capacities," he says. "We expect 40G revenue to increase at a compound annual growth rate (CAGR) of 59% from 2007 to
The SMI4027 and SMI4037 devices enable all common modulation formats in the 39.8-Gbps to 44.6-Gbps data range and incorporate a fully SFI-5-compliant client-side interface. Other features include ground-referenced high-speed differential output ports, high-speed differential clock outputs with low phase noise, and a SONET-compliant clock multiplier unit (CMU) with on-chip voltage controller oscillator (VCO). Additionally, the devices includes two user-selectable reference clock input ports and reference clock clean-up loop circuitry.
Rounding out the feature set for the MUX are a phase detector on-chip dual-mode (PRWS) error checker and pattern generator, a 512-bit arbitrary pattern generator, and an SPI control interface that supports a range of logic families, says the company. The SMI4037 Demux has clock and data recovery (CDR) and SONET-compliant clock jitter tolerance. The devices operate from dual-power supply voltages of +1.2V or +1.8V and -2.8V, with a combined low power consumption of just over 4 Watts typical (with high-speed clock outputs disabled) for the chipset.
The SMI4027 device is sampling now and scheduled to enter volume production in the second quarter of 2009. It is packaged in a ball grid array (BGA) with GPPO connectors.
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