Bit-stream duty cycle and optical transceiver performance

Sept. 1, 1998

Bit-stream duty cycle and optical transceiver performance

Alan Wolke amp Inc.

Some optical receiver designs suffer serious performance degradation when presented with data streams having wide or unbalanced duty cycles. The duty cycle of Fast Ethernet (100Base-FX), for example, ranges from 40% to 60%. If the data stream remains unbalanced at one of these extremes for a long time, a receiver could experience increased bit-error rates, pulsewidth distortion, and jitter.

In a serial bit pattern, duty cycle is the ratio of the number of ones or zeros to the total number of bits in a given bit stream. This is also often referred to as "duty factor." If the number of ones and zeros is equal, or balanced, the duty cycle is 50%.

Conversely, when the number of ones differs from the number of zeros in a bit stream, the data is unbalanced. The term "wide duty cycle range" applies to a data stream with a duty cycle that varies significantly from 50% for long periods of time.

Signaling and encoding schemes for networking generally attempt to maintain an average duty cycle of 50%. Several schemes string many bits together (long-run lengths) to achieve balance. An example is the pseudo-random bit sequence scrambling scheme in Synchronous Optical Network and Asynchronous Transfer Mode. Others trade off run length for duty cycle control, such as the 4B/5B substitution code used by Fast Ethernet and Fiber Distributed Data Interface (fddi). This scheme limits the run length but can only guarantee that the duty cycle remains between 40% and 60%.

Receiver front ends

Efforts to control duty cycle and run lengths are for the benefit of conventional optical receivers. The optical receiver must convert the optical pulses it receives to electric digital pulses. The optical signal is unipolar: the presence of optical power represents a logical one, and its absence represents zero. (In practice, a logic zero is often represented by a low level of optical power.)

In the optical receiver, the photodetector, usually a PIN photodiode, sees the incoming optical power. The detector converts this optical energy to a signal current that mimics the optical pulse. Preamplifiers boost the signal current and convert it to a voltage.

The amplitude of this voltage signal depends on three parameters: optical input power level, the detector responsivity (response in amps per watt of input power), and the gain of the amplifier or preamp. For most receivers in multimode local area network applications, the latter two parameters are fixed. So the voltage-pulse amplitude depends solely on the input power.

Typically, optical receivers operate with a wide range of optical input power levels: -14 dBm or more to -32 dBm or less for receivers operating at 125 to 155 Mbits/sec in local area network applications over multimode fiber.

Because the photodetector is a "square-law" device, these 18 dB of optical dynamic range corresponds to a 36-dB or greater dynamic range of the electrical signal amplitude. As a result, the output amplitude of the receiver`s front end can range from a couple of millivolts to nearly a volt or more.

Receiver back ends

The primary job of the receiver`s back end, often called the postamplifier or quantizer, is to reconstruct the serial digital data signal. It creates a voltage analog of the optical pulse stream. One voltage level represents a one, and another, a zero.

The quantizer slices the signal amplitude in half (its midpoint) along the time dimension. Whenever the signal level is above its midpoint, that represents a logic one. And when the signal is below its midpoint, that represents a logic zero. It functions like a comparator whose inputs are the signal and its midpoint.

For the quantizer to operate properly, it must accurately set the midpoint decision threshold, or "slicing" point for a given input signal. This threshold varies, depending upon the signal amplitude. As discussed earlier, the signal amplitude can vary by more than 36 dB. If the decision threshold set by the quantizer differs from the signal`s midpoint, the receiver suffers from reduced sensitivity and pulsewidth distortion.

The sensitivity of an optical receiver, or more accurately its bit-error-rate performance, depends on the signal-to-noise ratio (snr) presented to the comparator. As with many electronic devices, sensitivity improves (bit-error rate decreases) as the snr increases.

If the comparator`s decision threshold differs from the signal`s midpoint, the snr improves for one logic value but degrades for the other. So to maximize the snr (minimize bit-error rate) for detecting both a logic one and a zero, the threshold must be at the midpoint.

Pulsewidth distortion also increases as the decision threshold differs from the signal midpoint. This distortion results in a deviation of a logic transition from its ideal point in time. If the decision threshold rises or falls with respect to the signal, the time at which the comparator would detect the signal crossing the threshold changes (the voltage signal is more like a sine wave than a square digital pulse). This then moves the position of the digital transition from its ideal point in time, creating pulsewidth distortion.

Setting the decision threshold

So the decision threshold must be placed exactly at the signal midpoint to minimize bit-error rate and pulsewidth distortion. This maximizes receiver sensitivity and recovered signal integrity. But the signal amplitude can be anything from a few millivolts to nearly a volt or more.

If the data pattern has a 50% duty cycle, then the appropriate signal threshold is simply the average of the signal, regardless of the signal amplitude. In this case the receiver`s postamplifier must simply compare the signal level to its average.

Most implementations of optical receivers don`t perform this task explicitly, but simply AC-couple the signal to the comparator. In this way, the signal centers itself at the comparator with its average at the comparator reference (same result).

So, creating and transmitting data patterns with a 50% duty cycle greatly simplifies the design of the optical receiver. Nearly all optical receivers on the market today operate in this way or in a similar fashion.

This design must ensure that the receiver averages the signal over a long-enough period of time (its effective integration time). In this way, short-term duty cycle variations of consecutive ones or zeros don`t cause a shift in the decision threshold. These receivers do an excellent job if the long-term duty cycle remains near 50%. They have been serving the industry for nearly two decades.

On the other hand, these receiver designs suffer when the duty cycle differs from 50% for long periods (longer than their effective integration time). Under these conditions, the decision threshold essentially follows the duty cycle. This degrades sensitivity and produces pulsewidth distortion that varies with time, the very definition of jitter. Specifically, if the duty cycle of the signal varies widely enough for a long-enough period to result in a threshold shift, jitter results. This is called data-dependent jitter.

Fast Ethernet encoding

One encoding scheme that can result in such problems is that used by Fast Ethernet. The 100Base-FX standard employs a data-encoding scheme called 4B/5B. This scheme translates 4-bit nibbles of data into 5-bit symbols. This encoding method is inherited from fddi. The nature of the resulting serial bit stream is that its duty cycle varies between 40% and 60%.

The physical-layer device assembles the data to be transmitted into frames. It appends the necessary frame header/ preamble bits to the data packet, and follows the data with checksum bits. In between transmitted frames, it transmits idle bits. Idle symbol transmission has a 50% duty cycle. The length of the data packet of a frame (number of data symbols) is variable. This length ranges from 46 to 1500 bytes, which translates to a range of 460 to 15,000 serial, encoded, non-return-to-zero (nrz) bits.

The natural "randomness" of real- world data usually results in data packets that settle about the mean of a 50% duty cycle. However, this ideal situation does not always occur. It is entirely possible to have data packets that are unbalanced at either 40% or 60% duty cycle or somewhere in between.

These excursions from a 50% duty cycle occur readily when transmitting repetitive data. So sometimes long bit streams are unbalanced. For example, suppose the maximum length of a data packet is 1500 bytes. This is 3000 nibbles or symbols, which becomes 15,000 serialized bits. This amount of bits, at 8 nsec per bit, represents a data packet that is unbalanced for 120 microsec. Consecutive frames of similar data packets can result in a much longer duration of unbalanced bit streams over the fiber.

The eye diagrams of Figure 1 show measurements on commercially available 1 ¥ 9 transceiver modules, using a conventional receiver architecture operating at a bit rate of 125-Mbit/sec nrz. This architecture operates on the principle that the logical decision threshold in the receiver is the average of the data signal.

As indicated by the first eye pattern, a 50% duty cycle pattern presented to such a receiver produces acceptable output. This is because, under these conditions, the decision threshold rests at the average (50% point) of the data signal.

When this same receiver is tested with a data pattern having a 40% or 60% duty cycle, severe distortion in the pulsewidth occurs. Under these conditions, the decision threshold is at the signal`s average, which is not the signal`s midpoint. The design architecture of the receiver always produces a balanced output, regardless of the input.

These tests were carried out with continuous unbalanced data to illustrate this point. The tests represent the worst-case limiting condition as numerous unbalanced maximum length frames are consecutively transmitted.

Each manufacturer`s receiver differs in how long it can look at an unbalanced data stream before significant distortion occurs. The time until distortion occurs depends on the effective integration time constant in the receiver. Some manufacturers` receivers may result in this level of distortion with one maximum length (120 microsec) data packet of unbalanced code.

Receivers for wide duty cycles

Some optical receivers on the market have a design architecture that accommodates variations of the duty cycle. Certain patented quantizer designs, for example, exhibit minimal degradation in performance as a function of duty cycle. They operate acceptably with a range of continuous duty cycles extending from less than 10% to more than 90%--a level of performance that cannot be met with any conventional optical receivers.

This architecture does not rely on the average of the data signal to determine the decision threshold. Conceptually, these designs measure the level of the positive and negative voltage excursions. A circuit generates an effective decision threshold that is exactly midway between them. Changes in duty cycle don`t affect the measured voltage extremes.

Optical receivers based on this architecture exhibit minimal performance degradation and data-dependent jitter from duty cycle and run-length variations. They virtually eliminate problems associated with the 4B/5B encoding scheme of Fast Ethernet.

The eye diagrams of Figure 2 show the receiver output when presented with a 50% duty cycle pattern at a bit rate of 125 Mbits/sec. The two adjacent eye patterns represent the output of the receiver with a continuous 40% and 60% data pattern. The distortion present in these eye patterns is minimal, typically less than 0.4 nsec.

Most transceivers provide good performance at 50% duty cycles. But in applications where a wide range of duty cycles can be expected, transceivers specifically designed to handle this phenomenon may prove the only solution. u

Alan Wolke is manager of circuit development at the Lytel Div. of amp Inc. (Harrisburg, PA).

Sponsored Recommendations

Data Center Interconnection

June 18, 2024
Join us for an interactive discussion on the growing data center interconnection market. Learn about the role of coherent pluggable optics, new connectivity technologies, and ...

The Journey to 1.6 Terabit Ethernet

May 24, 2024
Embark on a journey into the future of connectivity as the leaders of the IEEE P802.3dj Task Force unveil the groundbreaking strides towards 1.6 Terabit Ethernet, revolutionizing...

The Pluggable Transceiver Revolution

May 30, 2024
Discover the revolution of pluggable transceivers in our upcoming webinar, where we delve into the advancements propelling 400G and 800G coherent optics. Learn how these innovations...

From 100G to 1.6T: Navigating Timing in the New Era of High-Speed Optical Networks

Feb. 19, 2024
Discover the dynamic landscape of hyperscale data centers as they embrace accelerated AI/ML growth, propelling a transition from 100G to 400G and even 800G optical connectivity...