Novel method synchronizes 40?Gbit/s packets
By Yvonne Carts–Powell
A novel method for packet–level system synchronization and address comparison in optical time–division multiplexing (OTDM) systems was recently demonstrated by Scott A. Hamilton and Bryan S. Robinson at MIT's Lincoln Laboratory (Lexington, MA).1 The technique relies on cascaded semiconductor–based optical logic gates operating at 50–Gbit/s line rates.
In ultrafast OTDM networks, which have the potential for burst data rates of more than 100 Gbit/s, several network tasks must be achieved optically because current electronics aren't fast enough. These tasks include packet synchronization and header address comparison at packet routers or receiver nodes. Hamilton and Robinson's system demonstrates all–optical processing of 40 Gbit/s data at 50 Gbit/s line rates in an OTDM network testbed. The packet–synchronization and address–comparison architecture uses two modelocked fiber lasers and two ultrafast nonlinear interferometer (UNI) optical logic gates (see figure). The 1550–nm network channel–control pulse train consists of synchronous global 10–Gbit/s clock interleaved between 40–Gbit/s data. A laser local to the receiver operating at 1545 nm provides a 10 Gbit/s signal pulse train to both UNIs.
System synchronization to packet timing is achieved at the UNI biased to act as a Boolean NAND gate. The NAND gate passes a single signal pulse at 1545 nm only when a missing packet reference pulse is present in the control stream at the UNI. This single missing pulse provides a temporal marker local to the receiver that signifies the beginning of a packet. It resists channel–induced timing delays, and can be adapted to asymmetric packet lengths and to multichannel OTDM transmission.
Experimental setup for all–optical packet synchronization and address comparison in OTDM networks. The 1550–nm modelocked fiber laser and packet generator provide network control inputs. The 1545–nm modelocked fiber laser provides local signal input. In the packet synchronization part of the system, both laser inputs are sent to an ultrafast nonlinear interferometer (UNI1) optical logic gate, which acts as a NAND gate. The two lasers are bit–phase synchronized by a dithering phase–locked loop (DPLL). In the address comparison part of the system, the output of the NAND gate is used by an address generator, which is then compared to the address information from the network at UNI2, which acts as an AND gate. Only if the addresses match is a signal passed on from this second logic gate.
The second UNI compares the local receiver address to the incoming network address in each packet. The researchers demonstrated four–bit all–optical address comparison at 40–Gbit/s data rates. The local address is generated from the single packet reference using standard optical multiplexing methods and temporally aligned to overlap one of the 10–Gbit/s interleaved network–packet address channels. Each network–packet address is compared bit by bit to the local–receiver address at the UNI with a 5–ps switching window biased for AND operation. When a bit match is achieved, the AND gate passes that bit. An address match is verified when four optical pulses are output from the address comparison UNI.
An extinction ratio of 7 dB is achieved between matched and unmatched address bits for the address–comparison with 19–fJ signal and 21–fJ control pulse train UNI switching energies. The UNI was stable over time periods longer than 1 h. The address space is scalable and unlimited. The researchers believe this method is scalable up to 200 Gbit/s line rates.
For more information contact Scott A. Hamilton at firstname.lastname@example.org.
1. S. A. Hamilton, B. S. Robinson, IEEE Photon. Tech. Lett. 14(2), 209 (February 2002).