Cortina and Cisco launch high-speed interconnect spec

April 3, 2006 Sunnyvale and San Jose, CA -- Cortina Systems and Cisco Systems today unveiled a jointly developed protocol specification for high-speed chip-to-chip packet transfers. Dubbed 'Interlaken,' the new technology leverages the best characteristics of both SPI4.2 and XAUI to enable higher performance--including 90% chip-to-chip signal trace improvement--and lower board and chip design costs, reports Lightwave's Senior News Editor, Meghan Fuller.

April 3, 2006 Sunnyvale and San Jose, CA -- Cortina Systems and Cisco Systems today unveiled a jointly developed protocol specification for high-speed chip-to-chip packet transfers. Dubbed 'Interlaken,' the new technology leverages the best characteristics of both SPI4.2 and XAUI to enable higher performance--including 90% chip-to-chip signal trace improvement--and lower board and chip design costs, reports Lightwave's Senior News Editor, Meghan Fuller.

There are three basic functions inside any networking line card. First, there's a device that interfaces to the external world or line side port and performs the electrical protocol conversion or Layer 1/Layer 2-type functions. Second is the packet processing engine, which determines where in the system each packet must egress. Finally, the traffic manager grooms the traffic from multiple sources and ensures that traffic is switched according to defined priorities. As system densities scale, the bandwidth required between these ICs increases correspondingly.

"Essentially, we needed a higher speed tool to enable those interconnections," reports Jim McKeon, product manager at Cortina Systems. "This is a roadmap or a methodology for designing high-speed interfaces beyond today's 10-Gbit standards."

The best of both worlds

Today, there are two tools used to design 10-Gbit/sec-class interfaces: SPI4.2 and XAUI.
A key benefit of SPI4.2 is the notion of virtual channelization, says McKeon. "You can chop the bandwidth into a large number of virtual channels and control the throughput on each of those channels independently," he explains. "It has this means for doing flow control on each of the different channels. We have found that there is widespread support for that kind of functionality within the industry."

That said, SPI4.2's parallel bus design makes for difficult alignment of the signals over long distances. Moreover, the design consumes in excess of 80 signal traces, rendering both the IC and the board more expensive. Employing multiple SPI4.2 interfaces to support high-speed applications is cost prohibitive and provides limited scalability.

The XAUI interface, by contrast, is based on robust Serdes technology. And it's efficient with only four pairs in each direction. However, the XAUI interface does not provide any virtual channelization functionality. It is a simple packet interface, "kind of a dumb pipe," admits McKeon.

Cortina and Cisco have created a new interface that builds upon the logical structure of SPI4.2, preserving its multiple logical channels, but runs over XAUI's more robust Serdes physical layer.

"The uniqueness is the flexibility and speeds," notes Mark Gustlin, technical leader in the Service Provider Routing Technology Group at Cisco. "SPI4 is essentially a 10-Gig interface, but [Interlaken] can scale. I envision it being used for 20-Gig applications first, maybe 24 Gig, scaling to 40 Gig and even 100 Gig is possible."

Unlike other interfaces, Interlaken works with any number of serial lanes, enabling designers to scale their implementation to a specific bandwidth requirement. "The bandwidth scales linearly with each lane, so if you have two lanes and you want to double your bandwidth, you go to four lanes. It's as simple and straightforward as that," says Gustlin.

The joint specification initially specifies an OIF-standard common electrical interface (CEI) up to 6-Gbit/sec Serdes, he reports. "Interlaken allows use of the latest 6-Gbit/sec serial technology in configurable increments, allowing designers to build interfaces that suit today's 20- to 40-Gbit/sec applications as well as the 100+Gbit/sec systems of tomorrow. The efficiency of this approach effectively removes the interface as a barrier to higher-density silicon and systems," Gustlin adds.

Interlaken preserves the SPI4.2 burst and packet control conventions; each packet is divided into smaller bursts, delineated by a burst header. The spec supports both full-packet mode and channel interleaving. A meta-frame guarantees lane alignment and clock compensation. Interlaken also provides in-band and out-of-band flow control.

Consider, for example, a five-lane bundle. "The interface is not necessarily a certain bandwidth, but it's conceptually a five-lane interface," explains Gustlin. "We take the packet stream, and we break it down into very small eight-byte chunks and we play those out across each lane sequentially. The first eight bytes would go to lane zero, the second eight bytes would go to lane one, lane two, etc., in a round-robin fashion. It's a very simple way of multiplexing the data across multiple lanes, filling all the lanes equally, and it allows us to design the hardware to be resilient to a lane going down," he says.

The Interlaken specification, named after a picturesque town in Switzerland that sits at the intersection of two lakes, is available with royalty-free licensing to interested parties developing next-generation Gigabit-speed routers and switches. For more information, contact Cortina Systems at interlaken@cortina-systems.com or Cisco Systems at interlaken@external.cisco.com.

--Meghan Fuller

More in Packet Transport