System design: Advantages of using merchant silicon in metro networks

By DAN HARDING
Sandburst Corporation

High-efficiency packet forwarding and switching are critical elements of metro area networks. Service providers are demanding greater functionality and higher bandwidth capacity in routers and switches to support new applications and services, as equipment manufacturers struggle to meet these requirements with fewer resources in a challenging economic environment.

The best way for switching and routing system designers to ease this pain and gain a competitive edge is through architectural flexibility at the design level. ASICs represent ultimate flexibility in system design, but development costs are extremely high and time-to-market can be painfully long. Generic network processors are flexible in that they can support a variety of network applications from TDM to ATM and Ethernet, but these devices cannot match the performance of a more targeted chip design.

A merchant silicon-based chipset that supports high per-port packet processing can provide this edge and drive a host of new networking innovations. By utilizing merchant silicon, system designers can focus on value, lower development costs, and pass the savings on to their service provider customers. Lowering the cost of deploying advanced Ethernet will ultimately drive service adoption.

Configurable, packet processing engines

Ethernet and IP switching and routing manufacturers have little opportunity to differentiate their products at the chip level. The technical requirements for Layer 2 and Layer 3 Ethernet switching and routing are well-defined, and about 90% of the technical requirements are the same for all manufacturers. Vendors largely differentiate chassis-based Ethernet switches and routers through services, software, and branding. As a result, internal chip development has become an unnecessary diversion of precious research and development resources.

With the cost to develop a single complex ASIC approximately $10 million, equipment vendors can more efficiently allocate resources by selecting merchant silicon solutions that provide the necessary high performance, wire-speed switching and routing as well as the ability to customize micro-code to add differentiation. By selecting a chip set that is tailored for packet switching and allows for micro-programmability, vendors can maintain the flexibility to support emerging standards and add their own "secret sauce" to differentiate their products. This customization capability is enabled by the use of micro-program code, or blocks of micro-instructions that implement custom packet handling features at line rate.

While Layer 2 and many Layer 3 Ethernet standards are well-established, Layer 3 Ethernet requirements at Gigabit and 10-Gbit/sec speeds, as well as standards for MPLS, IPv6 and IP services such as virtual private networks and voice over IP continue to evolve, making merchant silicon an optimum means of balancing features, development cycles, and cost points.

System developers work with the merchant silicon supplier to define unique requirements that are coded by the chip company to enable product differentiation. For example, a system manufacturer may want to define which fields in an Ethernet packet are inspected, how IP multicast or packet replication is implemented, or how the rules are defined in the forwarding database.

Architectural flexibility at the design level

Network switches for Ethernet and IP fall into two general categories: fixed port, "pizza box" platforms or modular, chassis-based systems with line cards. The fixed port platforms are relatively simple, and vendors differentiate these types of products primarily on brand value and price.

But chassis-based systems are more complex and merchant silicon provides the opportunity for vendors to reduce cost and accelerate time-to-market. Chips on the line cards communicate using integrated serializer/deserializer (SERDES) for full duplex, multi-channel data transport for high bandwidth integration to minimize component count and simplify backplane interconnection. While the PHY and MAC chips are largely commodities, the packet processor, traffic manager, and switch fabric interface chips are crucial elements for enabling architectural flexibility at the design level.

The packet processing engine receives the Ethernet packets from the MAC chip and determines where to send the packet and what priorities to apply based on rules that have been defined. The traffic manager than receives the packet and implements quality of service (QoS) guarantees, and a switch fabric interface chip sends and receives packets from the switch fabric. Some emerging components combine the traffic manager and switch fabric interface functions onto a single chip.

Scalability and programmability

The Ethernet market is extremely price-sensitive, but there are opportunities for new platforms using merchant silicon chipsets to create differentiation while reducing development costs and accelerating time-to-market. The key is to build on an architecture that offers the configurability necessary to differentiate a system and the scalability that can support the performance requirements of feature-rich IP services.

Systems developers can accelerate the delivery of 10-Gbit/sec, wire-speed equipment for the metropolitan area network and provide the robust QoS controls necessary for service providers to offer high-speed, business-class services. Switch and router equipment developers can select configurable chip set solutions and avoid large investments in development while maintaining maximum flexibility for incorporating emerging standards and addressing evolving feature requirements.

By leveraging an integrated data plane that includes hardware forwarding, queuing, and traffic management, vendors can avoid investments in custom ASICs and swiftly bring to market scalable 10-Gbit/sec per-port packet processing platforms. These systems can transport Ethernet and IP VPN services and offer robust protocol support for both virtual LAN and MPLS switching that can scale to capacities exceeding 1 Tbit/sec.