Infineon announces first RPR Draft 2.1-compliant chips

6 May 2003 Munich, Germany Lightwave--Infineon Technologies AG introduced a family of optical networking integrated circuits (ICs) that are the industry's first to comply with Draft 2.1 of the proposed IEEE 802.17 Resilient Packet Ring (RPR) standard.

6 May 2003 Munich, Germany Lightwave--Infineon Technologies AG introduced a family of optical networking integrated circuits (ICs) that are the industry's first to comply with Draft 2.1 of the proposed IEEE 802.17 Resilient Packet Ring (RPR) standard. The new Frea packet-over-SONET (PoS) Framer/RPR media access control (MAC) ICs are the latest addition to Infineon's portfolio of optical network solutions.

The single-chip Frea devices integrate functions previously requiring a minimum of four separate components. This is the highest degree of integration of any RPR chip, and can result in significant savings for manufacturers of switches and routers in terms of power consumption, board design complexity and space, software development, and overall system cost. For example, the bill of materials for a typical RPR node implementation, excluding memory, may be as high as $1,650, which is almost $300 greater than the high-end Frea chip. Even greater cost-of-ownership savings can be seen when the benefits of a smaller footprint, lower power, and use of a single software suite are considered.

RPR technology is used to support the use of high-speed Ethernet communications in optical network systems. The Frea chips perform the PoS framer, RPR MAC and XAUI SerDes(serializer/deserializer) functions that are necessary to deploy RPR in metropolitan area networks and wide area networks. These high integration ICs eliminate the need for external memory by including 1 Mbyte of memory on-chip for RPR operation and also a 16-bit 800 MHz SPI-4.2 system interface and a 4-bit 3.125 GHz mate (XAUI) interface, eliminating the need for an external SerDes to link the two chips required for a full RPR implementation.

"With its advantages in spatial reuse and Ethernet mapping efficiency, RPR has gained a foothold at North American MSOs [multiple system operators] and Chinese greenfield carriers. For RPR to gain broader acceptance, it must penetrate the significant installed base of legacy SONET/SDH systems at the LECs [local-exchange carriers]," said Allan Armstrong, director of Communications Semiconductors at telecom research and advisory firm RHK (South San Francisco). "By providing both RPR and SONET modes of operation, Infineon's Frea framer IC will help drive the acceptance of RPR by mitigating the risk of the SONET versus RPR decision for system vendors and carriers alike."

"The Frea chips represent yet another step in achieving our goal of delivering standards-based products to the broad packet data market," said Subodh Toprani, senior vice president and general manager of the Communications Business Group, Infineon Technologies.

Meanwhile, RPR technology, which is being standardized in the IEEE 802.17 committee, is gaining wide acceptance in systems that extend Gigabit Ethernet (GbE) into metro area and wide area networks. It is a Layer 2 MAC technology that combines the simplicity and bandwidth efficiency of Ethernet-based networks with the carrier-class features of SONET networks. For carriers, the RPR architecture can provide greater than a 50% cost reduction over the traditional PoS architecture, for example, by reducing the number of core router ports required to implement a network. RPR technology will play a critical role in allowing service providers to create high-speed networks that efficiently transport voice and data traffic while lowering both capital and on-going operational expenses.

During the early phases of the RPR standardization process, when the specifications were in a state of flux, solutions for the most part were in-house field-programmable gate array (FPGA) and network processor-based developments, with all the size, cost and other constraints typically associated with those approaches. However, the majority of the features that will appear in the final RPR specification have been firmed-up in Draft 2.1, so the move to cost-effective, high-integration, low-power application-specific standard products, such as the Frea PoS Framer/RPR MAC, is becoming very attractive to equipment manufacturers.

The PoS Framer/RPR MAC supports both the IEEE 802.17 RPR standard (Draft 2.1) and the RFC 2892 Spatial Reuse protocol (SRP), and is ideally suited to applications using either. It can also operate in a PoS framer-only mode, which gives carriers flexibility in building legacy PoS networks that can later be configured to RPR when the need arises through a simple software upgrade. This flexibility lowers the total cost of ownership for carriers deploying RPR networks.

Samples of the first two chips of the Frea PoS Framer/RPR MAC family, one operating at the OC-192 rate of 10 Gbits/sec and the other at the OC-48 rate of 2.5 Gbits/sec, will be available in July, with volume production planned for later in the year. Both chips are fabricated in .13-micron technology and available in a FCHBGA package. The 10-Gbit/sec version of the Frea IC, which has a power consumption of less than 8W, will be priced at $1,395 in volume quantities, and the 2.5-Gbit/sec version with a power consumption of less than 3.5W will be priced at $645 in volume quantities.

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