Silicon Labs intros single I/O any-rate clock multiplier

MARCH 25, 2008 -- The new Si5319 Any-Rate Precision Clock is capable of generating any output frequency from either a crystal or reference clock input with 0.3-psec jitter generation.

MARCH 25, 2008 -- Silicon Laboratories Inc. (search for Silicon Laboratories) has expanded its portfolio of reconfigurable, frequency-agile precision clocks to include a single input, single output jitter-attenuating clock multiplier IC. The new Si5319 Any-Rate Precision Clock is capable of generating any output frequency from either a crystal or reference clock input with 0.3-psec jitter generation.

The device supports a free-run mode of operation, enabling the device to be used as a frequency-flexible, low-jitter clock generator when supplied a crystal input. The Si5319 can provide clock synthesis, clock multiplication, and jitter attenuation in high-performance timing applications such as SONET/SDH/OTN line cards, WDM line cards, wireless base stations, synchronous Ethernet routers, test and measurement equipment, and broadcast video.

The Si5319 is based on Silicon Labs' patented, third generation DSPLL technology, which the company says provides any-rate frequency synthesis and jitter attenuation in a highly integrated phase-locked loop (PLL) approach that eliminates the need for external voltage-controlled crystal oscillator (VCXO) and loop filter components. The Si5319 can accept any frequency from 2 kHz to 710 MHz and generate any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz, according to the company.

The Si5319 is designed to provide a highly integrated, cost-effective jitter attenuation approach for next-generation multi-rate line cards that must support a broad array of client-side and line-side interfaces, including SONET/SDH, 1G/10G Ethernet, Fibre Channel, OTN, and HD-SDI. The company says the timing architecture is dramatically simplified because a single Si5319 can generate all required reference frequencies with extremely low jitter, eliminating the need for multiple high-frequency VCXOs.

The Si5319 free-run mode of operation greatly simplifies clock startup issues in high-performance applications, Silicon Labs adds. In these systems, customers typically use a high-frequency crystal oscillator (XO) to generate an initial reference clock for the transceiver driving the high-speed fiber-optic link. After initial startup, the system requires a reference clock that is synchronized to another clock in the system not available at startup. Traditional approaches require external multiplexer circuitry to switch between the high-frequency XO and the long-term reference clock.

The Si5319 solves this problem by locking to an inexpensive crystal input at startup and switching to an active input clock when available. No external mux components are required and the clock switchover is seamless, says the company. These factors minimize output clock phase transients that would otherwise generate bit-errors in the high speed fiber optic interface.

The Si5319 is available now in a 6x6-mm, 36-lead QFN package. The device is available in three speed grades based on maximum output clock frequency. Pricing for the lowest speed grade device, which supports a clock output frequency range of 2 kHz to 346 MHz, is $19.32 in quantities of 1,000.

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