Silicon Line debuts ultra-low-power physical layer chipset

JANUARY 22, 2008 -- The complete chipset exhibits a total power dissipation of below 10 mW, say Silicon Line representatives. This power number includes all necessary currents through the VCSEL as well as the power dissipated by the resistive output load connected to the TIA.

JANUARY 22, 2008 -- Silicon Line GmbH (search for Silicon Line), a German fabless analog IC company, today announced the release of a 2.5-Gbit/sec chipset comprising a transimpedance amplifier (TIA) with integrated limiting amplifier and a vertical-cavity surface-emitting laser (search for VCSEL) driver.

According to the company, the complete chipset exhibits a total power dissipation of below 10 mW. This power number includes all necessary currents through the laser as well as the power dissipated by the resistive output load connected to the TIA. The only power need of the VCSEL driver (SL82026) itself is far below 1 mW and that of the transimpedance amplifier (SL82016) is far below 5 mW, claim Silicon Line representatives.

"Optical data transmission based on polymer optical fibers or waveguides becomes more and more prevalent," notes Holger Hoeltke, managing director at Silicon Line. "Especially in mobile or portable electronics where massive EMI-constrains, bandwidth requirements, and mechanical issues challenge the traditional physical layer design, ultra-low power optical data transmission comes in as perfect alternative," he says. "With its PHY-layer chipset Silicon Line provides an enabling technology into these markets."

The chipset SL82016/SL82026 features sub-LVDS I/Os, which provide a differential output voltage of 200 mV. Upon request, Silicon Line says it provides to its VCSEL-driver a temperature controller, which automatically maintains over a wide temperature range a given extinction ratio for the VCSEL. Silicon Line's TIA, the SL82016, works together with either a GaAs photodiode or a Si photodiode. With a minimum input current of 20 uApp, the SL82016 allows for an optical input sensitivity of -16dBm at a BER of 10-12 at 2.5 Gbits/sec.

"Due to their excellent power efficiency, both chips may also be used for parallel optical links," adds Martin Groepl, Silicon Line's technical director. "With only a few adaptations, we may provide them as one-dimensional or two-dimensional arrays. With that, they're suitable for high-speed board-to-board, backplane, or chip-to-chip connections."

The SL82016 as well as the SL82026 exhibit a chip area of less than 0.5 mm(2). Both ICs are available in bare die form. Sampling of the ICs starts now.


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