JANUARY 27, 2009 -- Fujitsu Microelectronics Europe (FME; search for Fujitsu) has announced the availability of its new ADC IP based on Charge-mode Interleaved Sampler (CHAIS) technology for use in its standard 65-nm CMOS process technology. This new high-speed ADC technology is designed to provide breakthrough performance levels in a standard CMOS process, enabling the integration of multiple ADCs with tens of millions of gates of signal processing logic and memory on a single chip. Initially targeting use in coherent receivers for 100G optical transmission, the technology is also applicable to high-end test equipment and any other system requiring high-speed data conversion and processing.
FME asserts that the new CHAIS technology provides previously unachievable combinations of sampling rate, resolution, and power consumption. These circuits avoid many of the limiting factors, such as restricted bandwidth and poor linearity, of conventional architectures to make ADCs with sampling rates of up to 100 GSa/sec feasible in CMOS for the first time, the company claims.
Power consumption for the ADC is 2 W typical per channel at 56 GSa/sec at a performance level of ENOB>6. A half-speed mode provides 28 GSa/sec at 1 W per channel. A 1.75-GHz input reference clock is internally multiplied to provide ADC sampling clocks with less than 100 fsec total rms jitter and less than 500 fsec of I/Q ADC skew.
"With our new ADC technology in combination with the ability to integrate in excess of 50 million logic gates, we provide the enabling technology for upcoming telecom applications, such as 100G Ethernet and OTU-4", said Dirk Weinsziehr, vice president of marketing and development at FME. "Based on this technology our customers can build bespoke products with lower power consumption, higher integration, and a unique manufacturability to secure their leading position in the market."
The first production application of the ADC technology will be a single-chip DP-DQPSK coherent receiver for 100G optical networks, with four-channels of 56-GSa/sec 8-bit ADCs (I and Q signals, H and V polarisation) integrated with logic and memory to perform the complete receive PHY function when connected directly to the optical front-end.
A single-chip approach avoids the need to transfer terabits-per-second of data between ADC and DSP chips -- reducing power consumption, silicon area, and the number of I/O pins. The need for expensive multi-chip module (MCM) technology is eliminated, FME adds.
The increased ADC resolution and sampler dynamic range eases the design of the optical front-end by allowing part or all of the AGC function to be realised digitally after the ADC, the company says.
FME also says that continuous digital background self-calibration during operation means that external calibration test signals or non-volatile calibration memory are not required, and no user intervention is needed to achieve and maintain the specified performance levels.
"Current high-speed ADCs are mostly developed in a SiGe process technology. Products using such technology tend to suffer from high power consumption and limited integration with digital signal processing. We saw a strong demand from our customer base for high-performance data converters in standard CMOS technology," explained Neil Amos, director of the Communications Business Unit at FME. "With this groundbreaking ADC technology, Fujitsu now provides the option to integrate analogue conversion at GSa/sec and digital signal processing on the same die. Originally driven by telecom applications we now see increasing interest in test and measurement and high-speed interface applications."
The ADC will initially be available in 2009 in Fujitsu's CS200 65-nm process technology as two-channel and four-channel 56-GSa/sec 8-bit macro cells. Other channel counts, sampling rates, resolutions, and process nodes will follow according to market demands.
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