Altera ships FPGA for 40G/100G applications
JUNE 1, 2009 -- Altera Corp. has announced availability of what it asserts is the industry's highest density, highest system-bandwidth FPGA.
JUNE 1, 2009 -- Altera Corp. (search Lightwave for Altera) has announced availability of what it asserts is the industry's highest density, highest system-bandwidth FPGA. Featuring 11.3-Gbps transceivers and 530k logic elements (LEs), the Stratix IV GT EP4S40G5 and EP4S100G5 FPGAs are the latest variants of Altera's 40-nm Stratix IV FPGA family shipping to customers.
The Stratix IV GT FPGAs are designed to support 40G/100G technologies, including 40/100-Gigabit Ethernet (GbE) media access controllers (MACs), Optical Transport Network (OTN) framers and mappers, 40G/100G Enhanced Forward Error Correction (EFEC), and 10G chip-to-chip and chip-to-module bridging applications used in communications systems, high-end test equipment, and military communications systems.
"From a test perspective, building the 100G ecosystem requires reliable functionality from the physical layer upwards. The breadth and depth of 100G applications demands silicon solutions that offer sophisticated and deep functionality, high performance and density," said Jerry Gentile, senior vice president in JDSU's communications test and measurement business segment. "Supported by Altera's Stratix IV GT FPGAs, JDSU test solutions are ready for the comprehensive testing and validation of high-end communication systems with the ability to scale up to the latest communication solutions."
Altera says the Stratix IV GT devices are the only FPGAs that offer a single-chip approach featuring 11.3-Gbps integrated transceivers that can interface directly to a CFP optical module and meet the emerging IEEE 802.3ba standard for 100G MACs. The density and bandwidth in Stratix IV GT FPGAs provide designers of 40G/100G applications the flexibility to incorporate traffic management, packet processing, and their own custom functionality into a single device, the company asserts.
Stratix IV GT devices feature up to 48 integrated transceivers, a 0.9-V core power supply, on-die and on-packing decoupling, 20.7 Mbits of embedded memory, 1,024 18x18 multipliers, and up to 530,000 LEs. The devices support a wide variety of protocols and standards, including SFI-S, SFI-5.1, SFI-5.2, MLD, Interlaken, CEI-6G/11G, CAUI, and XLAUI and feature hard IP for PCIe Gen1 and Gen2 (x1, x4, x8).
The Stratix IV GT EP4S40G5 and EP4S100G5 devices are currently shipping, with other family members scheduled to ship in 2009.
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