Fujitsu Labs develops CMOS 40G transmitter IC
FEBRUARY 13, 2009 -- Three arms of Fujitsu have announced the development of what they tout as the world's first 65-nm standard CMOS -based transmitter IC (serializer) for 40-Gbps trunk-line optical transmission systems.
FEBRUARY 13, 2009 -- Fujitsu Laboratories Ltd., Fujitsu Laboratories of America Inc., and Fujitsu Ltd. (search Lightwave for Fujitsu) have announced the development of what they tout as the world's first 65-nm standard CMOS -based transmitter IC (serializer) for 40-Gbps trunk-line optical transmission systems. New circuit technologies were developed for the realization of high-speed signal-generation circuits capable of stable generation of 40-Gbps output signals within the power voltage fluctuation ranges required for practical use.
The transmitter integrates on a single chip the I/O interface, signal processing, and high-speed signal generation that are all necessary for 40-Gbps transmissions. The signal processing functions include:
- a data-recovery function that enables five 10-Gbps electrical signals to be received without error
- a function that accommodates timing errors between these five signals
- a function that synchronizes the timing of these signals.
The signal generation capabilities include a function that receives four 10-Gbps electrical signals and generates either two 20-Gbps electrical signals or one 40-Gbps electrical signal.
Fujitsu presented details of these technologies at the IEEE International Solid-State Circuits Conference 2009 (ISSCC 2009), held in San Francisco from February 8 to February 12.
Part of this research was conducted by the Optoelectronic Industry and Technology Development Association (OITDA) of Japan, under a contract from the New Energy and Industrial Technology Development Organization (NEDO) of Japan for its project, "Development of Next-generation High-efficiency Network Device Technology."
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The use of CMOS technology in such a circuit presented several challenges, according to Fujitsu. For example, to achieve performance equivalent to compound semiconductors, not only do the operational speeds of the data-transmitting circuits need to be accelerated, but the clock signals (which are provided to circuits to determine their operational timing) must operate at 20 GHz with low noise and sufficient amplitude. One major cause of amplitude degradation as the clock signals are distributed to the circuit is parasitic capacitance from interconnects and elements. Due to the fact that CMOS has higher parasitic capacitance than compound semiconductors, a way to minimize the impact of parasitic capacitance had to be found to suppress amplitude degradation of clock signals at 20 GHz.
Furthermore, transistor miniaturization lowers their breakdown voltage, thus limiting the usable power-supply voltage to 1 to 1.2 V. This means that a fluctuation in the power supply could prevent sufficient voltage from reaching the circuit, thereby disrupting stable operation.
Key challenges to reducing the cost of optical transmission systems under such fluctuating usage conditions have included the maintaining stable timing factors for the data signals and clock signals in circuits, and development of circuits that feature stable operation.
Clock-signal distribution technology: A new circuit technology was developed for the clock-distribution circuit in the transmitter IC. Loss of clock signal swing is compensated by using inductors that enable low-power distribution of a low-noise clock signal. Compensation via inductors is a conventional way to cancel parasitic capacitance. By focusing on the fact that clock signals in the transmitter IC use a single frequency, new high-speed technology was used in which the inductor compensates for the parasitic capacitance only in the frequency band around the signal frequency, thereby enabling low-noise, high-speed transmission of clock signals, with fewer circuit stages.
Automatic timing-adjustment technology: A new circuit technology has been applied to the output circuit, with which timing of the clock signal that controls circuit operation and the data signal that passes through the circuit are continually monitored to optimize the relationship between the two signals.
In this circuit technology, the monitoring and adjusting mechanisms are segregated from the data-signal transmission pathway, so that additional circuits needed to implement these mechanisms do not degrade the data-signal waveform. At the same time, the timing of the two signals is automatically coordinated to realize fast data signal transmissions with stable waveforms.
The output waveform of the IC implementing the newly developed technologies is stable and sharp, Fujitsu says; Fujitsu Laboratories asserts it has demonstrated that the IC can produce a reliable 40-Gbps data output signal (with a data error rate less than 10E-12, less than one error per trillion bits) over a commercial temperature and voltage variation range. These technologies have also been verified as being effective for fluctuations in operating temperature, in addition to effectiveness for power voltage fluctuations.
One-chip integration and new clock-distribution circuitry permit power consumption to be lowered to less than 2 W, one-third that of conventional transmitter ICs, Fujitsu adds. Since low-power operation reduces heat generation, it permits higher-density mounting of optical transceiver modules in optical transmission equipment. In addition, new transponders made using this technology will be roughly half the size of conventional devices, Fujitsu asserts, resulting in lower overall cost.
The transmitter IC also uses the SFI-5.2 interface, which has emerged as a standard in recent years for low-speed interfaces.
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