MoSys announces Bandwidth Engine ICs and serial chip-to-chip communications interface

Feb. 3, 2010
MoSys Inc., a provider of differentiated, high-density memory and high-speed interface (I/O) intellectual property (IP), unveiled a roadmap for its new Bandwidth Engine integrated circuit (IC). The new release will combine MoSys' patented 1T-SRAM high-density embedded memory with its ultra high-speed 10 Gigabits per second (Gbps) SerDes interface technology and an arithmetic logic unit (ALU).

FEBRUARY 2, 2010 -- MoSys Inc., a provider of differentiated, high-density memory and high-speed interface (I/O) intellectual property (IP), unveiled a roadmap for its new Bandwidth Engine integrated circuit (IC). The new release will combine MoSys' patented 1T-SRAM high-density embedded memory with its ultra high-speed 10 Gigabits per second (Gbps) SerDes interface technology and an arithmetic logic unit (ALU).

MoSys' Bandwidth Engine promises to deliver unparalleled bandwidth performance in next-generation networking systems for storing, manipulating and accessing packets, control information, and statistics at breakthrough rates.

MoSys also announced the expansion of its overall business model to become a fabless semiconductor company supplying high-performance ICs, in addition to differentiated IP.

For the past several years, processor performance in applications such as computing and networking has continued to nearly double every 18 months. During the same period, the performance of memory technology has not kept pace, creating a significant barrier to improving overall system performance. The Bandwidth Engine family of ICs represents a breakthrough for next-generation networking systems. The combination of the high-speed random access of a 1T-SRAM memory core with a serial I/O operating at 10 Gbps will enable a Bandwidth Engine device to provide up to two billion accesses per second, over twice the performance of designs utilizing memory technologies. To further boost system performance, the on-chip ALU will allow macro functions to be performed within the Bandwidth Engine, reducing iterations between the other packet processing ICs and a Bandwidth Engine.

MoSys expects the Bandwidth Engine to enable up to four times the throughput, two to four times the density, up to 40 percent lower power and system cost savings of up to 50 percent compared with today’s alternative solutions. MoSys expects to offer samples of the first Bandwidth Engine ICs in late 2010, with production quantities available in the second quarter of 2011.

MoSys is also introducing the GigaChip Interface, an open, CEI-11 compatible chip-to-chip interface to enable efficient serial chip-to-chip communications in high-speed networking systems. The Bandwidth engine ICs will feature the easily-implemented GigaChip Interface, which will be designed to achieve 90 percent payload bandwidth efficiency. MoSys is currently working with partner companies to create an ecosystem that will support the GigaChip Interface.

Visit MoSys


Sponsored Recommendations

New Optical Wavelength Service Trends

July 1, 2024
Discover how optical wavelength services are reshaping the telecom landscape, driven by rapid expansion and adoption of high-speed connections exceeding 100 Gbps, championed by...

ON TOPIC: Innovation in Optical Components

July 2, 2024
Lightwave’s latest on-topic eBook, sponsored by Anritsu, will address innovation in optical components. The eBook looks at various topics, including PCIe (Peripheral...

Data Center Interconnection

June 18, 2024
Join us for an interactive discussion on the growing data center interconnection market. Learn about the role of coherent pluggable optics, new connectivity technologies, and ...

AI’s magic networking moment

March 6, 2024
Dive into the forefront of technological evolution with our exclusive webinar, where industry giants discuss the transformative impact of AI on the optical and networking sector...