The road to SFP+: Examining module and system architectures
by Ryan Latchman and Bharat Tailor
SFP+ is the latest pluggable optical module form factor for use in 10-Gbit/sec Ethernet and 8.5-Gbit/sec Fibre Channel systems. The objectives of this new form factor are to increase density through its smaller footprint and provide a low-cost module to help enable increased adoption.
Semiconductor companies and module vendors have begun to offer products for this space that can be used in a number of potential system architectures. This article investigates these architectures as they apply to Fibre Channel and Ethernet and discusses the merits of each in relation to SFP+ objectives.
Figure 1 depicts block diagrams of typical SFP+ module designs targeted for Fibre Channel and Ethernet applications. Two variants of SFP+ are currently being specified. The limiting variant, which closely resembles current SFP modules, includes a laser driver, a TOSA, a ROSA, and a limiting amplifier. The second variant, which is primarily intended for 10-Gbit/sec Ethernet long-reach legacy multimode (LRM) applications, requires a linear optical receive path and is therefore referred to as the linear variant. A third variant that is compliant with SFP+, although not explicitly defined by the standard, is the retimed variant. This variant integrates CDR functionality within the Tx and/or Rx path and resolves signal integrity challenges inherent to many high-speed systems.
Current 10-Gbit/sec modules (300-pin, XENPAK, XPAK, X2, XFP) guarantee physical layer compliance to standards since the host board design has little or no impact on optical link performance. In contrast, SFP+ modules present relatively new challenges for IC, module, and system designers since standards compliance is determined by the interaction of the system, module, and ICs. The linear variant, where the binary 1/0 decisions are made outside the module, is arguably the most difficult to design with, while the retimed variant is comparatively easy.
Linear and limiting SFP+ modules require high-quality ASIC/SerDes transmitters because IEEE and Fibre Channel standards place strict requirements on the optical interface and linear/limiting module types have Tx paths that do not correct for timing jitter. The SFP+ specification has not defined the required jitter performance for the ASIC/SerDes to meet the compliance point B specification. Instead, only the jitter requirement at B is given. This introduces a design challenge for system vendors and host ASIC/SerDes providers to mutually guarantee performance over production (IC to IC variation and PCB build variation) and operating conditions (temperature, voltage, humidity, etc.)
The design challenge at compliance point B is heightened by the relatively low amount of permitted jitter at this interface, which must be allocated between the host and the IC. The current SFP+ draft permits a maximum of 0.1 UIpp (or 9.7 psec at 10.3125 Gbits/sec) of data-dependent jitter (DDJ) and 0.055 UIpp (or 5.3 psec at 10.3125 Gbits/sec) of pulsewidth shrinkage (PWS). In many respects, this level of jitter performance is comparable to what is required in SONET/SDH systems, which have a jitter generation requirement of 0.1 UIpp and operate at a physical layer that has not been able to achieve the low cost of Ethernet and Fibre Channel.
Guaranteeing this level of jitter will most likely involve statistical analysis and guard-banding. One must also allocate portions of this budget for contributors shown in the modified reference model in Fig. 2. Each of these contributors affects the implementation cost for non-retimed SFP+
Since deterministic jitter is not a scalar quantity (i.e., it has an associated phase), the combination of the aforementioned contributors plus an optical module, when measured in the lab, may be less than the sum of the individual jitter contributors. In this case, deterministic jitter components are cancelling each other out. This cancellation, however, is not controlled or monitored in typical IC/system production environments and is therefore difficult to rely on. Also, since SFP+ modules are pluggable, field installation could lead to uncertain performance. An arithmetic summing of peak-to-peak values should be considered. Module vendors must also consider the potential types of jitter that can be presented to the module and ensure a compliant output from the module.
In an effort to address the jitter contributors mentioned, some silicon vendors have designed host repeater ICs that are intended to minimize the burden on 10G serial ASICs. These ICs assist with SFI channel concerns through relative layout flexibility compared to ASICs, but do not solve them; standard compliance is still dependent on the interaction between the host, the SFI repeater, and the optical module. The SFI channel between the repeater and the laser driver will invariably introduce more jitter than if the repeater were right beside the laser driver inside the optical module.
These host and module design issues can be greatly simplified by putting a repeater (or CDR) in the transmit direction within the SFP+ module. This CDR would reset the jitter budget within the module, eliminating the need for an IC between the ASIC and the module in the Tx direction, and greatly relax the required jitter performance from the ASIC.
This corresponds to the retimed architecture depicted in Fig. 3. The CDR functionality does increase power consumption marginally within the SFP+ module, but modules can still meet the less than 1-W Power Level I requirement. The CDR provides a well proven host-module interface that ensures standards compliance by resetting the jitter budget within the optical module. When a CDR is present in the module, one can expect the equivalent performance and robustness from the SFP+ system as an X2/XFP system, which in turn lowers development, test, and manufacturing costs.
In the receive direction, SFP+ retimed, limiting, and linear interfaces differ significantly. In the limiting interface, a binary 1/0 decision is made in amplitude but not in time. This results in squaring of the waveform, but jitter from the signal after O-to-E conversion is still present at the SFP+ connector. This is reflected in the limiting output jitter specification for Fibre Channel and Ethernet (draft values 0.71 UIpp and 0.7 UIpp, respectively).
In addition to the large jitter permitted at the output of the limiting interface, a special type of jitter has been defined: PWS. This special type of jitter can be particularly challenging since narrower pulses get attenuated to a greater extent when transmitted over lossy media and therefore require much higher bandwidth circuitry to recover and properly interpret received data.
Figure 4 depicts the challenges associated with PWS for 8.5-Gbit/sec Fibre Channel. As shown from this sequence, the host must be able to accept the equivalent of a 13.3-Gbit/sec signal from the receive direction of the SFP+ optical module. This signal must then propagate over the host channel and be recovered by the host ASIC.
The 13.3-Gbit/sec signal represents a potential challenge for the host ASICs since it is further degraded by the SFI channel and has additional deterministic jitter and random jitter associated with it. Although ASICs typically have equalization functionality targeted at compensating for the SFI channel, the equalization function does not perfectly compensate for the channel, particularly at higher frequencies. The imperfect reconstruction of the signal results in less margin for error-free performance over all operating conditions. This analysis applies directly to the 10-Gbit/sec Ethernet limiting interface, which can be even more challenging than 8.5-Gbit/sec Fibre Channel because of the higher data rate and the longer fiber link distances.
It is worth noting that the PWS analysis discussed here does not take into account retime functionality in the Rx direction. When a CDR is present in the receive direction, the jitter at the SFP+ connector drops significantly from greater than 0.7 UIpp to less than 0.25 UIpp, with negligible PWS, as depicted in Fig. 5. The Rx CDR adds a marginal amount to the module power consumption but can still fit within SFP+ 1-W power consumption requirements, particularly when integrated with a limiting amplifier.
The host can therefore rely on a low-jitter, high-speed signal from the CDR-based SFP+ module for routing over the PCB to the ASIC. System designers only need to ensure adequate host performance with a stable, clean module output that has already determined physical layer standard compliance to a large extent by making 1/0 decisions in both amplitude and phase. This architecture also enables the maximum amount of host design integration and once again removes the issue of spreading standards compliance across the host-module interface.
The last receive interface type is called the linear interface because the entire input path is kept linear so electronic dispersion compensation (EDC) ICs on the host board can attempt to recover highly impaired signals. This module type is primarily targeted at 10-Gigabit Ethernet LRM applications, where signals must be sent over long distances of legacy multimode fiber. In the case of a linear interface, the received eye can be totally closed, making jitter measurements in terms of UI not meaningful. A new method of electrical test for this interface has therefore been introduced, which leverages LRM terms such as relative noise (RN) and waveform distortion penalty (WDP).
The linear module type shifts the majority of the standard compliance onto the host board since 1/0 decisions are not made within the module at all. In fact, this module class requires very good linearity in the receive path over all operating conditions. Even with optimal linearity, additional challenges arise due to crosstalk and SFI/module channel loss with reflections. This makes an already challenging LRM specification even more difficult to meet by placing the EDC chip on the host board and not within the module. Linear modules also typically have lower gain than limiting modules, making output amplitudes smaller and potentially more difficult for hosts to recover.
Properly designed EDC chips are, however, able to compensate for LRM stressors. Depending on margin, they may be able to be used for receive direction link compliance, although EDC can increase the power consumption and the cost of a serial PHY by a significant factor.
Each of the three architectures discussed in this article has an associated cost, power, and performance. The table summarizes the potential cost for each module type along with potential link support.
System, module, and IC designers have provided the high-speed communications market with a number of implementation options for SFP+. Depending on application performance and cost requirements, an implementation can benefit from some or all of these options. Having a solid physical layer design ensures standards compliance over operating conditions and production, and can provide system designers the flexibility for design changes to line cards without having to worry about the impact to the physical layer compliance or pluggable module interoperability.
Ryan Latchman is a senior product definition specialist and Bharat Tailor is a director of marketing in the Analog and Mixed Signal Products Division at Gennum (www.gennum.com).