EDC vendors try again on LRM

May 1, 2007

by Stephen Hardy

Critics of the 10GBase-LRM often warned of the difficulty of relying on electronic dispersion compensation (EDC) to push a serial 10-Gbit/sec data stream down 220 m of legacy 62.5-µm multimode fiber. Judging by how long it has taken X2 transceivers compliant with the LRM specifications to reach the market-and the fact that most of the first generation of these modules use an EDC chip from the same vendor, despite several supplier options-such predictions apparently proved sound. Nevertheless, the chip vendors have not given up. While licking the wounds generated during the first X2 skirmish, IC suppliers have begun to retool their offerings in hopes of earning future design wins, either for a “cost-reduction” design round in the X2 space or for the first generation of SFP+ applications.
While Vitesse cleaned up in the initial round of 10GBase-LRM X2 designs, a subsequent “cost reduction” round of designs offers other EDC vendors a second chance.

The 10GBase-LRM PHY was designed to offer a serial-and, hopefully, cheaper-alternative to four-channel 10GBase-LX4 modules for 10-Gigabit Ethernet applications over legacy fiber in enterprise and data center applications. LRM proponents touted EDC as the key to overcoming the dispersion inherent in such multimode fiber that previously had prevented practical serial transmission. However, difficulties soon became apparent when the working group charged with creating the specifications decided to abandon matching the 300-m reach of the LX4 in favor of a more manageable 220 m.

Nevertheless, several IC vendors-particularly startups-jumped into the market in hopes of meeting the EDC requirement. Vendors such as Aeluros (www.aeluros.com), Big Bear Networks (parts of which were acquired subsequently by Vitesse Semiconductor, Infinera, and Finisar), ClariPhy Communications (www.clariphy.com), Phyworks (www.phyworks-ic.com), Intersymbol Communications (acquired by Kodeos, which applied its technology to telco applications), Quake Technologies (eventually purchased by AMCC), Santel (now defunct), and Scintera Networks (www.scintera.com) had their names connected with EDC for LRM at one time or another. They competed with in-house efforts from such transceiver vendors as Intel (www.intel.com) and Avago Technologies (www. avagotech.com), as well as the difficulty of meeting the dispersion challenge on the one hand and the cost and power limitations transceiver multisource agreements (MSAs) and their potential customers imposed on the other.

Add to these challenges the lack of test equipment capable of determining whether devices were specification compliant (a problem only recently solved by Circadiant, www.circadiant.com, with competition now coming from Synthesys Research, www.bertscope.com) and the advent of the SFP+, which limited the opportunity for XFP business and gave them another MSA to worry about. It is little wonder that some EDC vendors complained about hitting a moving target. The supplier market fragmented somewhat, with some vendors (such as Scintera) offering a pure EDC device, others (such as Phyworks and Vitesse) offering combined EDC/CDR chips, and a third group (such as Aeluros and, after abandoning work on an EDC/CDR combination, AMCC/Quake) focusing on ICs that would combine EDC, CDR, and PHY capabilities and reside on the line card-just what SFP+ would require.

The uncertainty among the EDC community clearly affected the delivery of LRM-compliant transceivers. It’s customary that transceiver vendors will announce module availability before specifications reach final standardization; although the LRM PMD finally reached closure last fall, compliant X2 transceivers only made their debut during March’s OFC/NFOEC conference and exhibition. Vitesse (www.vitesse.com) crushed its competition in terms of design wins, announcing placement with five of the top six module vendors; according to at least one transceiver source at OFC/NFOEC, Vitesse’s chip was the only offering with sufficient margin to inspire confidence that it would work across the variety of legacy environments it was likely to face.

However, Vitesse won’t have a chance to rest on its laurels. SFP+ transceivers have already appeared, which means increasing pressure for EDC capabilities for LRM applications of these modules. The competition also looks forward to a new round of X2 designs intended to reduce costs and improve performance.

As noted previously (see “SFP+ Transceivers Emerge as Key 10GbE Trend,” Lightwave, December 2006, page 23), the SFP+ form factor has been positioned for many of the same applications as the XFP, particularly in the datacom space. The device, specifications for which have not reached completion, aims to save cost, space, and power consumption versus the XFP, largely by moving some of the functions contained within the XFP module onto the line card-including, in the case of LRM applications, the EDC.

For initial applications, the EDC likely will be combined with XAUI PHY and other functions. As already noted, both Aeluros and AMCC have positioned themselves with such devices. Aeluros initially offers a pair of single-channel devices, the SFI/XFI Puma AEL 2003 CDR/EDC and Puma AEL 2005 for XAUI/SFI LAN PHY/SerDes with EDC. Dual-channel examples of both devices should sample later this year.

The company does have design wins for the AEL2005, according to Siddharth Seth, director of marketing at Aeluros. Seth reports that while the SFP+ will reduce XFP datacom opportunities, it won’t remove them completely. He says system houses that have adopted XFP for their platforms will need to talk with LRM-enabled X2 modules, thus creating at least a small market for LRM modules in the XFP form factor.

AMCC, meanwhile, offers the QT1215, which integrates programmable mixed-signal EDC within an XFI-to-SFI bridge chip. The dual-port device has been sampling since January; the company expects to make the chip generally available this July. Meanwhile, the QT2035S, an SFI-to-XAUI PHY with EDC, also was on display at OFC/NFOEC.
The SFP+ changes the game for EDC vendors. Instead of being integrated within the transceiver, the EDC function must reside somewhere on the line card.

Other companies also plan to make a play within this application space. Vitesse, of course, will not be content with its X2 winnings. The company announced an SFP+ evaluation platform using its current VSC8238 EDC device, and asserted a new generation of chip with integrated PHY is on the way.

ClariPhy will offer an all-digital CMOS device that comprises a 10-gigasample/sec analog-to-digital converter (ADC) and a maximum likelihood sequence detection (MLSD) EDC engine. Although MLSD-type algorithms are very popular for EDC in the telco space, ClariPhy appears to be alone when it comes to offering this approach for LRM applications.

While ClariPhy touts its digital approach, Phyworks counters that the analog signal chain holds the key to LRM performance. Stephen King, Phyworks chief executive officer, Paul Denny, vice president, product development, and Brad Weaterton, director of marketing, concede that their EDC/CDR device didn’t meet their performance expectations for the original X2 round of designs. The company has refocused its efforts on a new generation of technology (like Vitesse, the company also makes transimpedance amplifiers for LRM applications as well) that it hopes to sample this summer.

Interestingly, Phyworks doesn’t plan to integrate PHY functions into its new device. Like others, the company expects the PHY function to be integrated into other devices, such as MACs, with serial interfaces becoming the norm. The expectation points up the fact that exactly what the SFP+ will demand remains uncertain. The onboard application offers a different set of challenges for EDC, in that it must combat any distortion created by the FR4 traces on the board as well as whatever dispersion the signal encountered reaching the transceiver. The amount of trace obviously has an effect on the dispersion and other noise the EDC will have to clean up. The specifications for EDC will come from the module working group, rather than the standards body that developed the LRM PMD-although clearly the specification makers won’t stray far from the general parameters set by the IEEE.

The target is much clearer for the anticipated round of “cost reduction” designs for X2. Chip vendors expect this round to get underway during the second half of this year, which gives them a few months to try to match the performance bar Vitesse has set. Naturally, the vendors contacted for this article expect success, including Scintera Networks. While the company declined to provide details on the record, Scintera did show new CMOS-based technology at its booth during OFC/NFOEC. A new product should be announced soon.

Is all this effort worth it? Clearly, these IC vendors believe so. Mitch Kahn, AMCC’s vice president of marketing for transport products, reports “good business” for X2 and XENPAK applications over the next two or three years, with perhaps as many as 10,000 LRM ports needed over the next 18 months. The SFP+ numbers remain undetermined, of course, but should provide a significant opportunity. Whether it proves enough to keep all of these companies in the game appears unlikely-particularly if one vendor wraps up the market again.

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