EDC continues to retain long-haul positioning

July 1, 2005

While much of the attention paid to electronic dispersion compensation (EDC) has focused on legacy 300-m multimode-fiber applications, the technology made its first splash as a potential enabler of 40-Gbit/sec networks. Several chip vendors have retained a focus on singlemode applications outside the enterprise, as recent product announcements for 10 Gbits/sec demonstrate. But even these vendors admit that the multimode opportunity may be too tempting to pass up.

As speeds increase, signals traveling within an optical fiber become more susceptible to the effects of chromatic and polarization mode dispersion (PMD). EDC was considered almost mandatory for 40-Gbit/sec networking. However, chip vendors say that, as carriers upgrade 2.5-Gbit/sec links to 10 Gbits/sec, dispersion issues may arise as well, particularly on older fibers. Thus, EDC will have a role to play in long-haul and metro networks well before the eventual jump to 40 Gbits/sec.

For this reason, Applied Micro Circuits Corp. (AMCC-San Diego) has followed up its work in pairing EDC with forward error correction (FEC) for singlemode links with a new device launched last February. The S19233 combines dual clock and data recovery (CDR) with EDC in a single 0.13-µm CMOS chip for rates of 9.9 to 11.3 Gbits/sec. It features specifications such as jitter tolerance of 0.8 UI and jitter generation of 35 mUI. AMCC aims the chip at XFP transceivers for Ethernet, Fibre Channel, SONET/SDH, and FEC applications.

According to Oswin Schreiber, senior product marketing manager at AMCC, the dual CDR configuration can save footprint and enable loopback capabilities. But for designers who don’t want two channels in one chip, AMCC can supply two chips, each with one active channel. The chip is now sampling, with volume production slated for the second half of this year.

Meanwhile, Broadcom (Irvine, CA) launched its own chip that combines CDR and EDC for 10-Gbit/sec singlemode applications. The BCM8105 consumes a little more than 1 W and provides 9.9-11.1-Gbit/sec CDR with an SFI-4 demultiplexer that incorporates an adaptive EDC equalizer. The chip compensates 3,000 psec/nm of chromatic dispersion and 50 psec of digital group delay caused by PMD.

Michael Furlong, product-line manager of Broadcom’s Networking Business Unit, says the 0.13-µm CMOS device pairs decision-feedback-equalizer (DFE) technology with the ability to create an adaptive loop, thus removing the need for FEC. Broadcom targets the chip (which is sampling) at applications of 80 km or more.

While these established companies build on existing analog product lines, startup Intersymbol Communications (Champaign, IL) will approach EDC from the digital domain. Its Smart-CDR device, due to begin production in the third quarter, leverages maximum likelihood sequence estimation (MLSE) technology to provide better performance than DFE or feedback forward equalization (FFE) approaches, according to company founder, president, and CEO Andrew Singer. MLSE examines a longer bit sequence than DFE or FFE and contains a longer memory of the sequences it has received, Singer says. As a result, the SmartCDR will be able to extract signals even when the signal eye is practically closed. Its performance over distance will also degrade more gradually than competitive approaches, enabling system and subsystem designers more flexibility in budgeting for dispersion penalties.

The SmartCDR combines an analog front end in SiGe with a digital backend in CMOS. The device supports a range of data rates from 9.953 to 12 Gbits/sec. Singer reports that 10.7 Gbits/sec “is a very popular number” and that 11.3 Gbits/sec “is a common one for some long-haul applications.” The chip currently consumes a little less than 4 W, although Singer reveals that the company has a program under way to reduce that figure to below 2.5 W.

That program aims to make the device compatible with the XFP multisource agreement-and while Singer anticipates that his product will find applications for metro applications within such transceivers, he admits that the company has its eye on 10GBase-LRM transceivers for 300 m over multimode fiber. Both Schreiber at AMCC and Furlong at Broadcom admit their companies also are looking to expand into the LRM space, a natural progression since many of the EDC vendors already targeting that module are either offering or working on CDR/EDC combination chips.

Quake Technologies (Kanata, Ontario) will also play both fiber sides, albeit with the same chip. XENPAK, XPAK, X2, and XFP module designers can apply the QT1006B1, slated to be unveiled this month, to either multimode or singlemode applications, according to product managers Rocco Matricardi and Marika Herod. The device will offer a CDR/EDC combination as well as retiming in support of data rates between 9.95 and 11.3 Gbits/sec. Internal algorithms enable the device to adapt itself to changing channel characteristics; alternatively, EDC performance can be controlled externally via a two-wire interface. The chip will combat differential mode delay as well as chromatic dispersion and PMD, although the Quake sources declined to reveal the techniques in use. Speaking before the product’s official release, they were also reluctant to quote a power dissipation figure.

So while EDC in the metro and long-haul is no longer just for 40 Gbits/sec, it appears that chip vendors will have a hard time resisting the carnival-like atmosphere that currently surrounds the enterprise multimode opportunity.

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