Santel Networks announces availability of 10-Gbit/sec electronic dispersion compensator with CDR-D on-chip
September 11, 2002--Santel Networks will ship samples of the world's first commercially available 10-Gbit/sec electronic dispersion compensator (EDC) product in November. The company will be previewing the two-chip set at NFOEC 2002 in Dallas, TX, from September 15th to 19th.
September 11, 2002--Santel Networks, provider of high-speed optical networking PHY ICs, will ship samples of what it claims is the world's first commercially available 10-Gbit/sec electronic dispersion compensator (EDC) product in November. The company will be previewing the S44501/S44003 two-chip set at the National Fiber Optic Engineers Conference (NFOEC) 2002 in Dallas, Texas from September 15th to 19th.
The S44501/S44003 10-Gbit/sec OC-192 chip set offers users substantial savings over equivalent optical solutions, contend company representatives. In the case of chromatic dispersion (CD) compensation, cost savings of up to 25% may be achieved, while much greater savings may be realized in the case of polarization mode dispersion (PMD) compensation. The major benefit of the S44501/S44003 chip set for telecom suppliers and service providers is that it provides an affordable electronic solution to mitigate the effects of signal distortion on high-speed optical networks. By mitigating distortions, optical network product designers are able to extend transmission distances, simplify network architectures, and improve network reliability. By comparison, optically based solutions can be prohibitively expensive and difficult to implement.
"Integrating electronic dispersion compensation onto a PHY IC is a big challenge to existing IC vendors," asserts Allan Armstrong, director of communications semiconductors at RHK Inc. (San Francisco). "Those who do not respond risk losing significant market share."
"Top tier service providers and network equipment vendors have evaluated early versions of our technology and are eager to test the integrated chip set of our electronic compensator because it will greatly reduce their system costs, and improve their system performance," adds Stefan Braken-Guelke, chief executive officer at Santel Networks. "Our development team has raised the bar for high-speed optical networking performance, with a semiconductor solution--a truly memorable event. We believe that our CleanSignal EDC technology will play an important role not just in 10-Gbit/sec OC-192 but also in extending the data capacity of networks to 40-Gbit/sec and beyond."
To accomplish this, the S44501/S44003 provides electronic dispersion compensation (EDC) capability along with all of the traditional clock and data recovery/demultiplexor (CDR-D) functions, at about the price of a high-end CDR-D IC. Santel's patented CleanSignal high-speed adaptive signal processing technology greatly mitigates the effects of optical signal degradation mechanisms such as CD, PMD, and other distortions that have traditionally stymied optical networking. CleanSignal technology enables the S44501/S44003 to double the chromatic dispersion tolerance in 10-Gbit/sec networks.
By compensating for signal distortions introduced during transmission through optical fiber, the highly integrated two-chip set increases signal quality, which can effectively extend the transmission distance range of existing transponders and enables the utilization of legacy fiber.
The chip set accepts a 9.95- to 12.5-Gbit/sec bit stream from an optical receiver. Its advanced integrated clock recovery circuit uses advanced VCO and PLL techniques to produce a stable clock from even severely distorted signals. The CleanSignal technology performs high-speed adaptive equalization that actively filters out the effect of the signal distortions. The EDC then outputs demultiplexed 16 bit data words synchronized to the recovered clock signal output, enabling subsequent forward error correction (FEC), multiplexer, or other client-side device to process the data from the CleanSignal DSE.
The 3.3-Volt chip set meets the jitter tolerance requirements of GR-1377-CORE and is OIF 99.102 compliant. The signal conditioner chip is packaged in a 196-pin (15mm x 15mm) ball grid array (BGA) package, while the CMOS controller is housed in a 256-pin (17mm x17mm) BGA package. The chip set is priced at under $500 in production volumes. Engineering samples will be available in November and the company expects production volume availability in the first quarter of 2003.