Socionext offers transceiver chip for 100-Gbps DMT transmission

Communications semiconductor vendor Socionext Inc. has unveiled the MB8AJ2060, a fully integrated transceiver to support single-wavelength 100-Gbps optical transmission based on discrete-multitone (DMT) modulation. The device consumes less than 5 W, the company says.
March 17, 2016
2 min read

Communications semiconductor vendor Socionext Inc. has unveiled the MB8AJ2060, a fully integrated transceiver to support single-wavelength 100-Gbps optical transmission based on discrete-multitone (DMT) modulation. The device consumes less than 5 W, the company says.

Socionext sees a future in DMT-based transmission as a lower-cost alternative to coherent transmission in 100-Gbps data center interconnect applications at distances it describes as "a few tens of kilometers." It also believes the technology can apply to the support of 4G and 5G wireless services distribution.

"OFDM-based communications technologies like DMT, using individually modulated, orthogonal carriers, have been successful in overcoming limitations of legacy modulation formats where low-cost, higher data capacity is the goal. DVB-T, xDSL, and LTE were all enabled using OFDM," said Manfred Mettendorff, senior director, marketing and business management at Socionext. "Proven, leading-edge mixed-signal IPs, designed by Socionext's Network SoC BU in Europe and Japan, now take this approach a major step forward for fiber-optic networks."

Features of the DMT PHY include:

  • On-chip hardware for analog/digital conversion interface to optics, DMT modulation/demodulation, FEC processing, and high-speed SerDes electrical interface
  • Protocol agnostic, transparent pass-through of client data signals
  • Support of multiple 100 Gbps class clients (100 Gigabit Ethernet, ODU4, OTU4, 128GFC)
  • CAUI-4/OTL4.4/CPRI supported on client-side interface
  • Flexible data rates, including 25G, 50G, and 100G on the line side
  • Support of client-side sub-rates such as 4x25G, 2x50G, and 1x75G
  • Selectable low latency on-chip FEC
  • Link Communication Channel (LCC)
  • End-to-end link negotiation and management
  • Hitless, in-operation link diagnostics and reconfiguration
  • Integrated CPU subsystem
  • Device initialization and link training
  • Link management and non-real time DMT algorithms
  • On-chip, low-speed DAC for optics control

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