20 January 2003 -- Munich-based Infineon Technologies says it is now shipping to network equipment makers its single-chip Titan 768MD (announced in June 2002), a flexible, multi-function IC in a 680-pin BGA package for 10-40Gbit/s line-cards that can perform both interface conversion and serialiser/deserialiser (SerDes) operations.
"By providing sixteen 4:1 serializers with deskew in a standard product, Infineon lets switch and line-card designers remove a key risk element from their designs," says Allan Armstrong, director of communications semiconductors at industry analyst firm RHK Inc. "Whether they use ASICs or programmable logic, moving the high-speed interface off-chip allows them to use a less-expensive, lower risk technology."
"The Titan 768MD has an inherently flexible architecture that allows it to be immediately useful as both a high-density SerDes in legacy systems and an interface converter in advanced switching and routing equipment," said Christian Scherp, vice president of marketing in the Optical Networking Business Unit at Infineon Technologies North America Corp. "Our customers are taking advantage of this flexibility to enhance today's data communication systems, while looking at the potential for the same chip to provide scalable performance in future SONET systems with 10 and 40Gbit/s channel data rates."
Infineon claims that the Titan 768MD is ideal for use in a variety of SONET and datacom applications, including in 40Gbit/s OC-768 line-cards to perform SerDes Framer Interface Level 4 (SFI-4)-to-Level 5 (SFI-5) interface conversion. When performing narrowband SFI-5-to-SFI-4 conversion, 40Gbit/s data throughput can be achieved in both directions across a network while leveraging investments in 10Gbit/s framers. In addition, the IC can perform inverse multiplexing of the OC-768c payload from a router. When used with a high-speed framer and pointer processor, such as the Titan 19244, the 768MD provides a two-chip OC-768 solution for line-cards operating at a 40Gbit/s throughput.
The Titan 768MD can also function as a high-density serialiser/deserialiser in router/switch line-cards and backplanes to aggregate as many as 64 622Mbit/s channels into up to 16 2.5Gbit/s channels, or to convert the 2.5Gbit/s channels into 622Mbit/s outputs. The chip allows OEMs to continue using legacy systems in which core logic is implemented as field-programmable gate arrays (FPGAs) with 622Mbit/s interfaces, and provides a cost-effective migration path to higher-rate line-cards.
Integrated into the Titan 768MD are robust clock and data recovery (CDR) mechanisms, skew compensation functions and a clock synthesis mechanism. Diagnostic features include Pseudo Random Binary Sequence (PRBS) generation and checking, digital loop-back capabilities and support for IEEE 1149.1 JTAG testing. In addition, a microprocessor interface allows a CPU to access the registers for re-set, set-up, read, load, or to invoke built-in test functions.