SDAccel is aimed at building co-processors to accelerate functions such as encryption, search, speech recognition, and image recognition. The basic architecture has a board of UltraScale FPGAs that communicate with the server CPU cores via PCIe and have access to memory. Xilinx says this results in a 20-25X improvement in performance per watt compared to directly using the CPU or GPU and a 50-75X reduction in latency versus a pure software solution.
With SDAccel, software developers can leverage the benefits of FPGAs without having an understanding of the hardware or FPGA place or route. No prior FPGA experience is needed. In addition, Xilinx uses high-level synthesis (HLS) technology so SDAccel is able to support several languages, including C, C++, and Open CL. The SDAccel developer environment incorporates foundational compiler technology used by more than 1000 programmers, Xilinx says. Developers can create high-performance accelerators, optimized for memory, dataflow, and loop pipelining, that are suitable for data center applications including compute search, image recognition, machine learning, transcoding, storage compression, and encryption.
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